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/arch/powerpc/platforms/512x/
Dclock-commonclk.c70 static struct clk *clks[MPC512x_CLK_LAST_PRIVATE]; variable
403 for (i = 0; i < ARRAY_SIZE(clks); i++) in mpc512x_clk_preset_data()
404 clks[i] = ERR_PTR(-ENODEV); in mpc512x_clk_preset_data()
446 clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1); in mpc512x_clk_setup_ref_clock()
447 calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]); in mpc512x_clk_setup_ref_clock()
461 clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq); in mpc512x_clk_setup_ref_clock()
650 div = clk_get_rate(clks[MPC512x_CLK_SYS]); in mpc512x_clk_setup_mclk()
651 div /= clk_get_rate(clks[MPC512x_CLK_IPS]); in mpc512x_clk_setup_mclk()
674 clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed( in mpc512x_clk_setup_mclk()
681 clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated( in mpc512x_clk_setup_mclk()
[all …]
/arch/arm/boot/dts/
Dimx27.dtsi72 clocks = <&clks IMX27_CLK_CPU_DIV>;
95 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
96 <&clks IMX27_CLK_DMA_AHB_GATE>;
106 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
113 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
114 <&clks IMX27_CLK_PER1_GATE>;
122 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
123 <&clks IMX27_CLK_PER1_GATE>;
131 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
132 <&clks IMX27_CLK_PER1_GATE>;
[all …]
Dimx25.dtsi95 clocks = <&clks 48>;
106 clocks = <&clks 48>;
116 clocks = <&clks 75>, <&clks 75>;
125 clocks = <&clks 76>, <&clks 76>;
134 clocks = <&clks 120>, <&clks 57>;
143 clocks = <&clks 121>, <&clks 57>;
153 clocks = <&clks 48>;
163 clocks = <&clks 51>;
174 clocks = <&clks 78>, <&clks 78>;
185 clocks = <&clks 102>;
[all …]
Dvfxxx.dtsi93 clocks = <&clks VF610_CLK_DMAMUX0>,
94 <&clks VF610_CLK_DMAMUX1>;
102 clocks = <&clks VF610_CLK_FLEXCAN0>,
103 <&clks VF610_CLK_FLEXCAN0>;
112 clocks = <&clks VF610_CLK_UART0>;
124 clocks = <&clks VF610_CLK_UART1>;
136 clocks = <&clks VF610_CLK_UART2>;
148 clocks = <&clks VF610_CLK_UART3>;
162 clocks = <&clks VF610_CLK_DSPI0>;
177 clocks = <&clks VF610_CLK_DSPI1>;
[all …]
Dimx6sx.dtsi81 clocks = <&clks IMX6SX_CLK_ARM>,
82 <&clks IMX6SX_CLK_PLL2_PFD2>,
83 <&clks IMX6SX_CLK_STEP>,
84 <&clks IMX6SX_CLK_PLL1_SW>,
85 <&clks IMX6SX_CLK_PLL1_SYS>;
142 clocks = <&clks IMX6SX_CLK_PLL3_USB_OTG>;
166 clocks = <&clks IMX6SX_CLK_OCRAM_S>;
172 clocks = <&clks IMX6SX_CLK_OCRAM>;
198 clocks = <&clks IMX6SX_CLK_GPU>,
199 <&clks IMX6SX_CLK_GPU>,
[all …]
Dimx6qp.dtsi12 clocks = <&clks IMX6QDL_CLK_OCRAM>;
18 clocks = <&clks IMX6QDL_CLK_OCRAM>;
26 clocks = <&clks IMX6QDL_CLK_PRE0>;
35 clocks = <&clks IMX6QDL_CLK_PRE1>;
44 clocks = <&clks IMX6QDL_CLK_PRE2>;
53 clocks = <&clks IMX6QDL_CLK_PRE3>;
61 clocks = <&clks IMX6QDL_CLK_PRG0_APB>,
62 <&clks IMX6QDL_CLK_PRG0_AXI>;
70 clocks = <&clks IMX6QDL_CLK_PRG1_APB>,
71 <&clks IMX6QDL_CLK_PRG1_AXI>;
[all …]
Dimx51.dtsi83 clocks = <&clks IMX5_CLK_CPU_PODF>;
102 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
130 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
140 clocks = <&clks IMX5_CLK_IPU_GATE>,
141 <&clks IMX5_CLK_IPU_DI0_GATE>,
142 <&clks IMX5_CLK_IPU_DI1_GATE>;
179 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
180 <&clks IMX5_CLK_DUMMY>,
181 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
190 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
[all …]
Dimx6ul.dtsi79 clocks = <&clks IMX6UL_CLK_ARM>,
80 <&clks IMX6UL_CLK_PLL2_BUS>,
81 <&clks IMX6UL_CLK_PLL2_PFD2>,
82 <&clks IMX6UL_CA7_SECONDARY_SEL>,
83 <&clks IMX6UL_CLK_STEP>,
84 <&clks IMX6UL_CLK_PLL1_SW>,
85 <&clks IMX6UL_CLK_PLL1_SYS>;
141 clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
184 clocks = <&clks IMX6UL_CLK_APBHDMA>;
195 clocks = <&clks IMX6UL_CLK_GPMI_IO>,
[all …]
Dimx53.dtsi56 clocks = <&clks IMX5_CLK_ARM>;
121 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
129 clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
146 clocks = <&clks IMX5_CLK_SATA_GATE>,
147 <&clks IMX5_CLK_SATA_REF>,
148 <&clks IMX5_CLK_AHB>;
159 clocks = <&clks IMX5_CLK_IPU_GATE>,
160 <&clks IMX5_CLK_IPU_DI0_GATE>,
161 <&clks IMX5_CLK_IPU_DI1_GATE>;
221 clocks = <&clks IMX5_CLK_GPU3D_GATE>, <&clks IMX5_CLK_GARB_GATE>;
[all …]
Dimx6qdl.dtsi78 clocks = <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
169 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
178 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
179 <&clks IMX6QDL_CLK_GPMI_APB>,
180 <&clks IMX6QDL_CLK_GPMI_BCH>,
181 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
182 <&clks IMX6QDL_CLK_PER1_BCH>;
196 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
197 <&clks IMX6QDL_CLK_HDMI_ISFR>;
222 clocks = <&clks IMX6QDL_CLK_GPU3D_AXI>,
[all …]
Dimx35.dtsi81 clocks = <&clks 51>;
92 clocks = <&clks 53>;
101 clocks = <&clks 9>, <&clks 70>;
110 clocks = <&clks 9>, <&clks 71>;
121 clocks = <&clks 52>;
132 clocks = <&clks 68>;
145 clocks = <&clks 35 &clks 35>;
155 clocks = <&clks 56>;
175 clocks = <&clks 9>, <&clks 72>;
187 clocks = <&clks 36 &clks 36>;
[all …]
Dimx6sll.dtsi68 clocks = <&clks IMX6SLL_CLK_ARM>,
69 <&clks IMX6SLL_CLK_PLL2_PFD2>,
70 <&clks IMX6SLL_CLK_STEP>,
71 <&clks IMX6SLL_CLK_PLL1_SW>,
72 <&clks IMX6SLL_CLK_PLL1_SYS>;
113 clocks = <&clks IMX6SLL_CLK_PLL3_USB_OTG>;
167 clocks = <&clks IMX6SLL_CLK_SPDIF_GCLK>,
168 <&clks IMX6SLL_CLK_OSC>,
169 <&clks IMX6SLL_CLK_SPDIF>,
170 <&clks IMX6SLL_CLK_DUMMY>,
[all …]
Dimx31.dtsi77 clocks = <&clks 33>;
87 clocks = <&clks 35>;
97 clocks = <&clks 26>;
105 clocks = <&clks 10>, <&clks 30>;
114 clocks = <&clks 10>, <&clks 31>;
123 clocks = <&clks 34>;
133 clocks = <&clks 10>, <&clks 53>;
146 clocks = <&clks 46>;
153 clocks = <&clks 10>, <&clks 49>;
163 clocks = <&clks 10>, <&clks 50>;
[all …]
Dimx6q.dtsi42 clocks = <&clks IMX6QDL_CLK_ARM>,
43 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
76 clocks = <&clks IMX6QDL_CLK_ARM>,
77 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
78 <&clks IMX6QDL_CLK_STEP>,
79 <&clks IMX6QDL_CLK_PLL1_SW>,
80 <&clks IMX6QDL_CLK_PLL1_SYS>;
[all …]
Dimx7s.dtsi75 clocks = <&clks IMX7D_CLK_ARM>;
96 clocks = <&clks IMX7D_USB_PHY1_CLK>;
103 clocks = <&clks IMX7D_USB_HSIC_ROOT_CLK>;
158 clocks = <&clks IMX7D_PLL_SYS_MAIN_CLK>;
180 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
207 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
222 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
257 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
280 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
295 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
[all …]
Dimx6sl.dtsi69 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
70 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
71 <&clks IMX6SL_CLK_PLL1_SYS>;
100 clocks = <&clks IMX6SL_CLK_PLL3_USB_OTG>;
124 clocks = <&clks IMX6SL_CLK_OCRAM>;
168 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
169 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
170 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
171 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
172 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
[all …]
Dimx50.dtsi91 clocks = <&clks IMX5_CLK_USB_PHY1_GATE>;
122 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
123 <&clks IMX5_CLK_DUMMY>,
124 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
134 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
135 <&clks IMX5_CLK_DUMMY>,
136 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
146 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
147 <&clks IMX5_CLK_UART3_PER_GATE>;
158 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
[all …]
Dimx1.dtsi51 clocks = <&clks IMX1_CLK_MCU>;
82 clocks = <&clks IMX1_CLK_HCLK>,
83 <&clks IMX1_CLK_PER1>;
91 clocks = <&clks IMX1_CLK_HCLK>,
92 <&clks IMX1_CLK_PER1>;
100 clocks = <&clks IMX1_CLK_DUMMY>,
101 <&clks IMX1_CLK_DUMMY>,
102 <&clks IMX1_CLK_PER2>;
111 clocks = <&clks IMX1_CLK_HCLK>,
112 <&clks IMX1_CLK_PER1>;
[all …]
Dimx6dl.dtsi37 clocks = <&clks IMX6QDL_CLK_ARM>,
38 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
39 <&clks IMX6QDL_CLK_STEP>,
40 <&clks IMX6QDL_CLK_PLL1_SW>,
41 <&clks IMX6QDL_CLK_PLL1_SYS>;
67 clocks = <&clks IMX6QDL_CLK_ARM>,
68 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
69 <&clks IMX6QDL_CLK_STEP>,
70 <&clks IMX6QDL_CLK_PLL1_SW>,
71 <&clks IMX6QDL_CLK_PLL1_SYS>;
[all …]
Dimx6q-logicpd.dts60 &clks {
61 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
62 <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
63 <&clks IMX6QDL_CLK_IPU1_DI0_PRE_SEL>,
64 <&clks IMX6QDL_CLK_IPU2_DI0_PRE_SEL>;
65 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
66 <&clks IMX6QDL_CLK_PLL5_VIDEO_DIV>,
67 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
68 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>;
Datlas6.dtsi28 clocks = <&clks 12>;
64 clks: clock-controller@88000000 { label
85 clocks = <&clks 42>;
99 clocks = <&clks 5>;
106 clocks = <&clks 32>;
120 clocks = <&clks 34>;
131 clocks = <&clks 35>;
146 clocks = <&clks 32>;
160 clocks = <&clks 33>;
181 clocks = <&clks 9>;
[all …]
Dpxa27x.dtsi35 clocks = <&clks CLK_NONE>;
42 clocks = <&clks CLK_USBHOST>;
50 clocks = <&clks CLK_PWM0>;
57 clocks = <&clks CLK_PWM1>;
64 clocks = <&clks CLK_PWM0>;
71 clocks = <&clks CLK_PWM1>;
78 clocks = <&clks CLK_PWRI2C>;
88 clocks = <&clks CLK_USB>;
96 clocks = <&clks CLK_KEYPAD>;
109 clocks = <&clks CLK_CAMERA>;
[all …]
Dprima2.dtsi30 clocks = <&clks 12>;
75 clks: clock-controller@88000000 { label
96 clocks = <&clks 42>;
110 clocks = <&clks 5>;
117 clocks = <&clks 32>;
137 clocks = <&clks 35>;
152 clocks = <&clks 32>;
166 clocks = <&clks 33>;
187 clocks = <&clks 9>;
195 clocks = <&clks 8>;
[all …]
/arch/powerpc/boot/dts/
Dmpc5121.dtsi50 clocks = <&clks MPC512x_CLK_MBX_BUS>,
51 <&clks MPC512x_CLK_MBX_3D>,
52 <&clks MPC512x_CLK_MBX>;
67 clocks = <&clks MPC512x_CLK_NFC>;
134 clks: clock@f00 { label
159 clocks = <&clks MPC512x_CLK_BDLC>,
160 <&clks MPC512x_CLK_IPS>,
161 <&clks MPC512x_CLK_SYS>,
162 <&clks MPC512x_CLK_REF>,
163 <&clks MPC512x_CLK_MSCAN0_MCLK>;
[all …]
Dmpc5125twr.dts99 clks: clock@f00 { // Clock control label
129 clocks = <&clks MPC512x_CLK_BDLC>,
130 <&clks MPC512x_CLK_IPS>,
131 <&clks MPC512x_CLK_SYS>,
132 <&clks MPC512x_CLK_REF>,
133 <&clks MPC512x_CLK_MSCAN0_MCLK>;
141 clocks = <&clks MPC512x_CLK_BDLC>,
142 <&clks MPC512x_CLK_IPS>,
143 <&clks MPC512x_CLK_SYS>,
144 <&clks MPC512x_CLK_REF>,
[all …]

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