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Searched refs:cru (Results 1 – 25 of 159) sorted by relevance

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/external/u-boot/drivers/clk/rockchip/
Dclk_rv1108.c65 static int rkclk_set_pll(struct rv1108_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
69 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
117 static uint32_t rkclk_pll_get_rate(struct rv1108_cru *cru, in rkclk_pll_get_rate() argument
123 struct rv1108_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
143 static int rv1108_mac_set_clk(struct rv1108_cru *cru, ulong rate) in rv1108_mac_set_clk() argument
145 uint32_t con = readl(&cru->clksel_con[24]); in rv1108_mac_set_clk()
150 pll_rate = rkclk_pll_get_rate(cru, CLK_GENERAL); in rv1108_mac_set_clk()
152 pll_rate = rkclk_pll_get_rate(cru, CLK_ARM); in rv1108_mac_set_clk()
160 rk_clrsetreg(&cru->clksel_con[24], MAC_CLK_DIV_MASK, in rv1108_mac_set_clk()
168 static int rv1108_sfc_set_clk(struct rv1108_cru *cru, uint rate) in rv1108_sfc_set_clk() argument
[all …]
Dclk_rk3308.c66 struct rk3308_cru *cru = priv->cru; in rk3308_armclk_set_clk() local
82 priv->cru, APLL); in rk3308_armclk_set_clk()
85 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
87 rk_clrsetreg(&cru->clksel_con[0], in rk3308_armclk_set_clk()
95 rk_clrsetreg(&cru->clksel_con[0], in rk3308_armclk_set_clk()
103 priv->cru, APLL, hz)) in rk3308_armclk_set_clk()
107 return rockchip_pll_get_rate(&rk3308_pll_clks[APLL], priv->cru, APLL); in rk3308_armclk_set_clk()
114 priv->cru, DPLL); in rk3308_clk_get_pll_rate()
117 priv->cru, VPLL0); in rk3308_clk_get_pll_rate()
120 priv->cru, VPLL1); in rk3308_clk_get_pll_rate()
[all …]
Dclk_rk3288.c144 static int rkclk_set_pll(struct rk3288_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
148 struct rk3288_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
175 static int rkclk_configure_ddr(struct rk3288_cru *cru, struct rk3288_grf *grf, in rkclk_configure_ddr() argument
205 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
208 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg]); in rkclk_configure_ddr()
215 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK, in rkclk_configure_ddr()
298 static int rockchip_mac_set_clk(struct rk3288_cru *cru, uint freq) in rockchip_mac_set_clk() argument
306 if (readl(&cru->cru_clksel_con[21]) & RMII_EXTCLK_MASK) { in rockchip_mac_set_clk()
310 u32 con = readl(&cru->cru_clksel_con[21]); in rockchip_mac_set_clk()
325 rk_clrsetreg(&cru->cru_clksel_con[21], MAC_DIV_CON_MASK, in rockchip_mac_set_clk()
[all …]
Dclk_px30.c285 struct px30_cru *cru = priv->cru; in px30_i2c_get_clk() local
290 con = readl(&cru->clksel_con[49]); in px30_i2c_get_clk()
294 con = readl(&cru->clksel_con[49]); in px30_i2c_get_clk()
298 con = readl(&cru->clksel_con[50]); in px30_i2c_get_clk()
302 con = readl(&cru->clksel_con[50]); in px30_i2c_get_clk()
315 struct px30_cru *cru = priv->cru; in px30_i2c_set_clk() local
323 rk_clrsetreg(&cru->clksel_con[49], in px30_i2c_set_clk()
330 rk_clrsetreg(&cru->clksel_con[49], in px30_i2c_set_clk()
337 rk_clrsetreg(&cru->clksel_con[50], in px30_i2c_set_clk()
344 rk_clrsetreg(&cru->clksel_con[50], in px30_i2c_set_clk()
[all …]
Dclk_rk3188.c85 static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
89 struct rk3188_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
119 static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, in rkclk_configure_ddr() argument
149 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
152 rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj); in rkclk_configure_ddr()
159 rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, in rkclk_configure_ddr()
165 static int rkclk_configure_cpu(struct rk3188_cru *cru, struct rk3188_grf *grf, in rkclk_configure_cpu() argument
198 rk_clrsetreg(&cru->cru_mode_con, APLL_MODE_MASK << APLL_MODE_SHIFT, in rkclk_configure_cpu()
201 rkclk_set_pll(cru, CLK_ARM, &apll_cfg[cfg], has_bwadj); in rkclk_configure_cpu()
208 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_configure_cpu()
[all …]
Dclk_rk3128.c38 static int rkclk_set_pll(struct rk3128_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
42 struct rk3128_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
140 static void rkclk_init(struct rk3128_cru *cru) in rkclk_init() argument
147 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
153 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); in rkclk_init()
154 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); in rkclk_init()
167 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
172 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
190 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
195 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
[all …]
Dclk_rk322x.c41 static int rkclk_set_pll(struct rk322x_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
45 struct rk322x_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
79 static void rkclk_init(struct rk322x_cru *cru) in rkclk_init() argument
86 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
92 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); in rkclk_init()
93 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); in rkclk_init()
106 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
111 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
129 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
134 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
[all …]
Dclk_rk3328.c206 static void rkclk_set_pll(struct rk3328_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
216 pll_con = cru->apll_con; in rkclk_set_pll()
220 pll_con = cru->dpll_con; in rkclk_set_pll()
224 pll_con = cru->cpll_con; in rkclk_set_pll()
228 pll_con = cru->gpll_con; in rkclk_set_pll()
232 pll_con = cru->npll_con; in rkclk_set_pll()
256 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_SLOW << mode_shift); in rkclk_set_pll()
276 rk_clrsetreg(&cru->mode_con, mode_mask, PLL_MODE_NORM << mode_shift); in rkclk_set_pll()
279 static void rkclk_init(struct rk3328_cru *cru) in rkclk_init() argument
285 rk3328_configure_cpu(cru, APLL_600_MHZ); in rkclk_init()
[all …]
Dclk_rk3368.c61 static uint32_t rkclk_pll_get_rate(struct rk3368_cru *cru, in rkclk_pll_get_rate() argument
66 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_pll_get_rate()
88 static int rkclk_set_pll(struct rk3368_cru *cru, enum rk3368_pll_id pll_id, in rkclk_set_pll() argument
91 struct rk3368_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
130 static void rkclk_init(struct rk3368_cru *cru) in rkclk_init() argument
134 rkclk_set_pll(cru, APLLB, &apll_b_init_cfg); in rkclk_init()
135 rkclk_set_pll(cru, APLLL, &apll_l_init_cfg); in rkclk_init()
141 rkclk_set_pll(cru, GPLL, &gpll_init_cfg); in rkclk_init()
142 rkclk_set_pll(cru, CPLL, &cpll_init_cfg); in rkclk_init()
145 apllb = rkclk_pll_get_rate(cru, APLLB); in rkclk_init()
[all …]
Dclk_rk3399.c421 void rk3399_configure_cpu_l(struct rk3399_cru *cru, in rk3399_configure_cpu_l() argument
429 rkclk_set_pll(&cru->apll_l_con[0], apll_l_cfgs[apll_l_freq]); in rk3399_configure_cpu_l()
443 rk_clrsetreg(&cru->clksel_con[0], in rk3399_configure_cpu_l()
450 rk_clrsetreg(&cru->clksel_con[1], in rk3399_configure_cpu_l()
456 void rk3399_configure_cpu_b(struct rk3399_cru *cru, in rk3399_configure_cpu_b() argument
464 rkclk_set_pll(&cru->apll_b_con[0], apll_b_cfgs[apll_b_freq]); in rk3399_configure_cpu_b()
478 rk_clrsetreg(&cru->clksel_con[2], in rk3399_configure_cpu_b()
485 rk_clrsetreg(&cru->clksel_con[3], in rk3399_configure_cpu_b()
508 static ulong rk3399_i2c_get_clk(struct rk3399_cru *cru, ulong clk_id) in rk3399_i2c_get_clk() argument
514 con = readl(&cru->clksel_con[61]); in rk3399_i2c_get_clk()
[all …]
Dclk_rk3036.c44 static int rkclk_set_pll(struct rk3036_cru *cru, enum rk_clk_id clk_id, in rkclk_set_pll() argument
48 struct rk3036_pll *pll = &cru->pll[pll_id]; in rkclk_set_pll()
78 static void rkclk_init(struct rk3036_cru *cru) in rkclk_init() argument
85 rk_clrsetreg(&cru->cru_mode_con, in rkclk_init()
91 rkclk_set_pll(cru, CLK_ARM, &apll_init_cfg); in rkclk_init()
92 rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg); in rkclk_init()
105 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
110 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
128 rk_clrsetreg(&cru->cru_clksel_con[0], in rkclk_init()
133 rk_clrsetreg(&cru->cru_clksel_con[1], in rkclk_init()
[all …]
/external/u-boot/arch/arm/dts/
Drk3288.dtsi7 #include <dt-bindings/clock/rk3288-cru.h>
79 clocks = <&cru ARMCLK>;
80 resets = <&cru SRST_CORE0>;
86 resets = <&cru SRST_CORE1>;
92 resets = <&cru SRST_CORE2>;
98 resets = <&cru SRST_CORE3>;
115 clocks = <&cru ACLK_DMAC2>;
126 clocks = <&cru ACLK_DMAC1>;
138 clocks = <&cru ACLK_DMAC1>;
169 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
[all …]
Drk3399.dtsi6 #include <dt-bindings/clock/rk3399-cru.h>
77 clocks = <&cru ARMCLKL>;
85 clocks = <&cru ARMCLKL>;
93 clocks = <&cru ARMCLKL>;
101 clocks = <&cru ARMCLKL>;
110 clocks = <&cru ARMCLKB>;
118 clocks = <&cru ARMCLKB>;
165 clocks = <&cru ACLK_DMAC0_PERILP>;
175 clocks = <&cru ACLK_DMAC1_PERILP>;
190 clocks = <&cru ACLK_PCIE>, <&cru ACLK_PERF_PCIE>,
[all …]
Drk3328.dtsi6 #include <dt-bindings/clock/rk3328-cru.h>
41 // clocks = <&cru ARMCLK>;
134 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
146 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
158 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
178 clocks = <&cru SCLK_SPDIF>, <&cru HCLK_SPDIF_8CH>;
202 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
217 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
232 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
254 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
[all …]
Drk3xxx.dtsi45 clocks = <&cru ACLK_DMA1>;
56 clocks = <&cru ACLK_DMA1>;
68 clocks = <&cru ACLK_DMA2>;
96 clocks = <&cru CORE_PERI>;
103 clocks = <&cru CORE_PERI>;
121 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
132 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
146 clocks = <&cru HCLK_OTG0>;
162 clocks = <&cru HCLK_OTG1>;
179 clocks = <&cru HCLK_EMAC>, <&cru SCLK_MAC>;
[all …]
Dpx30.dtsi6 #include <dt-bindings/clock/px30-cru.h>
46 clocks = <&cru ARMCLK>;
58 clocks = <&cru ARMCLK>;
70 clocks = <&cru ARMCLK>;
82 clocks = <&cru ARMCLK>;
209 clocks = <&cru HCLK_HOST>,
210 <&cru HCLK_OTG>,
211 <&cru SCLK_OTG_ADP>;
216 clocks = <&cru HCLK_SDMMC>,
217 <&cru SCLK_SDMMC>;
[all …]
Drk322x.dtsi10 #include <dt-bindings/clock/rk3228-cru.h>
35 resets = <&cru SRST_CORE0>;
42 clocks = <&cru ARMCLK>;
49 resets = <&cru SRST_CORE1>;
56 resets = <&cru SRST_CORE2>;
63 resets = <&cru SRST_CORE3>;
79 clocks = <&cru ACLK_DMAC>;
133 clocks = <&cru SCLK_I2S1>, <&cru HCLK_I2S1_8CH>;
148 clocks = <&cru SCLK_I2S0>, <&cru HCLK_I2S0_8CH>;
161 clocks = <&cru SCLK_I2S2>, <&cru HCLK_I2S2_2CH>;
[all …]
Drk3036.dtsi7 #include <dt-bindings/clock/rk3036-cru.h>
54 clocks = <&cru ARMCLK>;
55 resets = <&cru SRST_CORE0>;
61 resets = <&cru SRST_CORE1>;
78 clocks = <&cru ACLK_DMAC2>;
100 cru: clock-controller@20000000 { label
101 compatible = "rockchip,rk3036-cru";
106 assigned-clocks = <&cru PLL_GPLL>;
117 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
130 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
[all …]
Drk3308.dtsi7 #include <dt-bindings/clock/rk3308-cru.h>
45 clocks = <&cru ARMCLK>;
192 clocks = <&cru SCLK_I2C0>, <&cru PCLK_I2C0>;
205 clocks = <&cru SCLK_I2C1>, <&cru PCLK_I2C1>;
218 clocks = <&cru SCLK_I2C2>, <&cru PCLK_I2C2>;
231 clocks = <&cru SCLK_I2C3>, <&cru PCLK_I2C3>;
244 clocks = <&cru PCLK_WDT>;
253 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
266 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
279 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
[all …]
Drv1108.dtsi9 #include <dt-bindings/clock/rv1108-cru.h>
68 clocks = <&cru ACLK_DMAC>;
88 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
102 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
116 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
132 clocks = <&cru SCLK_USBPHY>;
161 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
176 cru: clock-controller@20200000 { label
177 compatible = "rockchip,rv1108-cru";
187 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
[all …]
Drk3368.dtsi43 #include <dt-bindings/clock/rk3368-cru.h>
233 rockchip,cru = <&cru>;
250 clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
251 <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
262 clocks = <&cru HCLK_SDIO0>, <&cru SCLK_SDIO0>,
263 <&cru SCLK_SDIO0_DRV>, <&cru SCLK_SDIO0_SAMPLE>;
274 clocks = <&cru HCLK_EMMC>, <&cru SCLK_EMMC>,
275 <&cru SCLK_EMMC_DRV>, <&cru SCLK_EMMC_SAMPLE>;
287 clocks = <&cru SCLK_SARADC>, <&cru PCLK_SARADC>;
295 clocks = <&cru SCLK_SPI0>, <&cru PCLK_SPI0>;
[all …]
Drk3128.dtsi10 #include <dt-bindings/clock/rk3128-cru.h>
65 clocks = <&cru ARMCLK>;
175 clocks = <&cru ACLK_DMAC2>;
234 clocks = <&cru SCLK_NANDC>,
235 <&cru HCLK_NANDC>,
236 <&cru SRST_NANDC>;
246 cru: clock-controller@20000000 { label
248 compatible = "rockchip,rk3128-cru";
253 assigned-clocks = <&cru PLL_GPLL>;
264 clocks = <&cru SCLK_UART0>, <&cru PCLK_UART0>;
[all …]
/external/u-boot/doc/device-tree-bindings/clock/
Drockchip,rk3188-cru.txt9 - compatible: should be "rockchip,rk3188-cru", "rockchip,rk3188a-cru" or
10 "rockchip,rk3066a-cru"
23 preprocessor macros in the dt-bindings/clock/rk3188-cru.h and
24 dt-bindings/clock/rk3066-cru.h headers and can be used in device tree sources.
42 cru: cru@20000000 {
43 compatible = "rockchip,rk3188-cru";
60 clocks = <&cru SCLK_UART0>;
/external/u-boot/arch/arm/mach-rockchip/px30/
Dpx30.c219 static struct px30_cru * const cru = (void *)CRU_BASE; in board_debug_uart_init() local
223 rk_clrsetreg(&cru->clksel_con[34], in board_debug_uart_init()
226 rk_clrsetreg(&cru->clksel_con[35], in board_debug_uart_init()
244 rk_clrsetreg(&cru->clksel_con[40], in board_debug_uart_init()
247 rk_clrsetreg(&cru->clksel_con[41], in board_debug_uart_init()
273 rk_clrsetreg(&cru->clksel_con[46], in board_debug_uart_init()
276 rk_clrsetreg(&cru->clksel_con[47], in board_debug_uart_init()
295 rk_clrsetreg(&cru->clksel_con[37], in board_debug_uart_init()
298 rk_clrsetreg(&cru->clksel_con[38], in board_debug_uart_init()
/external/u-boot/arch/arm/mach-rockchip/rk3368/
Drk3368.c65 struct rk3368_cru *cru = rockchip_get_cru(); in mcu_init() local
80 rk_clrsetreg(&cru->clksel_con[12], MCU_PLL_SEL_MASK | MCU_CLK_DIV_MASK, in mcu_init()
85 rk_clrreg(&cru->softrst_con[1], MCU_PO_SRST_MASK | MCU_SYS_SRST_MASK); in mcu_init()
124 struct rk3368_cru * const cru = in sgrf_init() local
149 rk_setreg(&cru->softrst_con[1], DMA1_SRST_REQ); in sgrf_init()
150 rk_setreg(&cru->softrst_con[4], DMA2_SRST_REQ); in sgrf_init()
155 rk_clrreg(&cru->softrst_con[1], DMA1_SRST_REQ); in sgrf_init()
156 rk_clrreg(&cru->softrst_con[4], DMA2_SRST_REQ); in sgrf_init()

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