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Searched refs:DestReg (Results 1 – 25 of 288) sorted by relevance

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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp63 const DebugLoc &dl, unsigned DestReg, in emitThumb1LoadConstPool() argument
76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
83 const DebugLoc &dl, unsigned DestReg, in emitThumb2LoadConstPool() argument
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
111 (isARMLowRegister(DestReg) || Register::isVirtualRegister(DestReg)) && in emitLoadConstPool()
113 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
116 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
126 const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
131 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
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DThumb1InstrInfo.cpp40 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
46 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
50 || !ARM::tGPRRegClass.contains(DestReg)) in copyPhysReg()
51 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
61 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg) in copyPhysReg()
73 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
107 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
112 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) && in loadRegFromStackSlot()
116 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
125 BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) in loadRegFromStackSlot()
DThumb2InstrInfo.cpp123 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
126 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
127 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
129 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
179 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
191 BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
203 if (Register::isVirtualRegister(DestReg)) { in loadRegFromStackSlot()
205 MRI->constrainRegClass(DestReg, &ARM::GPRPairnospRegClass); in loadRegFromStackSlot()
209 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
210 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
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/external/llvm-project/llvm/lib/Target/ARM/
DThumbRegisterInfo.cpp63 const DebugLoc &dl, unsigned DestReg, in emitThumb1LoadConstPool() argument
76 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
83 const DebugLoc &dl, unsigned DestReg, in emitThumb2LoadConstPool() argument
95 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, Register DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
110 assert((isARMLowRegister(DestReg) || DestReg.isVirtual()) && in emitLoadConstPool()
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
125 const DebugLoc &dl, Register DestReg, Register BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
130 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
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DThumb1InstrInfo.cpp40 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
46 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
50 || !ARM::tGPRRegClass.contains(DestReg)) in copyPhysReg()
51 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
61 BuildMI(MBB, I, DL, get(ARM::tMOVSr), DestReg) in copyPhysReg()
73 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
107 Register DestReg, int FI, in loadRegFromStackSlot() argument
112 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) && in loadRegFromStackSlot()
116 (Register::isPhysicalRegister(DestReg) && isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
125 BuildMI(MBB, I, DL, get(ARM::tLDRspi), DestReg) in loadRegFromStackSlot()
DThumb2InstrInfo.cpp136 Register DestReg = MI.getOperand(0).getReg(); in optimizeSelect() local
138 if (!DestReg.isVirtual()) in optimizeSelect()
142 get(ARM::t2CSEL), DestReg) in optimizeSelect()
154 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
157 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
158 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
160 BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
210 Register DestReg, int FI, in loadRegFromStackSlot() argument
222 BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
234 if (Register::isVirtualRegister(DestReg)) { in loadRegFromStackSlot()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/SystemZ/
DSystemZPostRewrite.cpp89 Register DestReg = MBBI->getOperand(0).getReg(); in selectLOCRMux() local
91 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectLOCRMux()
110 Register DestReg = MBBI->getOperand(0).getReg(); in selectSELRMux() local
113 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectSELRMux()
120 if (DestReg != Src1Reg && DestReg != Src2Reg) { in selectSELRMux()
123 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
125 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
126 Src1Reg = DestReg; in selectSELRMux()
130 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
132 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
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/external/llvm-project/llvm/lib/Target/SystemZ/
DSystemZPostRewrite.cpp89 Register DestReg = MBBI->getOperand(0).getReg(); in selectLOCRMux() local
91 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectLOCRMux()
110 Register DestReg = MBBI->getOperand(0).getReg(); in selectSELRMux() local
113 bool DestIsHigh = SystemZ::isHighReg(DestReg); in selectSELRMux()
120 if (DestReg != Src1Reg && DestReg != Src2Reg) { in selectSELRMux()
123 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
125 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
126 Src1Reg = DestReg; in selectSELRMux()
130 TII->get(SystemZ::COPY), DestReg) in selectSELRMux()
132 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
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/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp42 const DebugLoc &DL, unsigned DestReg, in copyPhysReg() argument
48 assert(ARM::GPRRegClass.contains(DestReg, SrcReg) && in copyPhysReg()
52 || !ARM::tGPRRegClass.contains(DestReg)) in copyPhysReg()
53 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
66 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
98 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
102 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
103 isARMLowRegister(DestReg))) && "Unknown regclass!"); in loadRegFromStackSlot()
106 (TargetRegisterInfo::isPhysicalRegister(DestReg) && in loadRegFromStackSlot()
107 isARMLowRegister(DestReg))) { in loadRegFromStackSlot()
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DThumb2InstrInfo.cpp114 const DebugLoc &DL, unsigned DestReg, in copyPhysReg() argument
117 if (!ARM::GPRRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
118 return ARMBaseInstrInfo::copyPhysReg(MBB, I, DL, DestReg, SrcReg, KillSrc); in copyPhysReg()
120 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::tMOVr), DestReg) in copyPhysReg()
169 unsigned DestReg, int FI, in loadRegFromStackSlot() argument
183 AddDefaultPred(BuildMI(MBB, I, DL, get(ARM::t2LDRi12), DestReg) in loadRegFromStackSlot()
192 if (TargetRegisterInfo::isVirtualRegister(DestReg)) { in loadRegFromStackSlot()
194 MRI->constrainRegClass(DestReg, in loadRegFromStackSlot()
199 AddDReg(MIB, DestReg, ARM::gsub_0, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
200 AddDReg(MIB, DestReg, ARM::gsub_1, RegState::DefineNoRead, TRI); in loadRegFromStackSlot()
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DThumbRegisterInfo.cpp64 const DebugLoc &dl, unsigned DestReg, in emitThumb1LoadConstPool() argument
77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
84 const DebugLoc &dl, unsigned DestReg, in emitThumb2LoadConstPool() argument
96 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
105 const DebugLoc &dl, unsigned DestReg, unsigned SubIdx, int Val, in emitLoadConstPool() argument
110 assert((isARMLowRegister(DestReg) || isVirtualRegister(DestReg)) && in emitLoadConstPool()
112 return emitThumb1LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
115 return emitThumb2LoadConstPool(MBB, MBBI, dl, DestReg, SubIdx, Val, Pred, in emitLoadConstPool()
125 const DebugLoc &dl, unsigned DestReg, unsigned BaseReg, int NumBytes, in emitThumbRegPlusImmInReg() argument
129 bool isHigh = !isARMLowRegister(DestReg) || in emitThumbRegPlusImmInReg()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FixupLEAs.cpp367 Register DestReg = MI.getOperand(0).getReg(); in optTwoAddrLEA() local
372 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA()
388 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
390 if (DestReg != BaseReg) in optTwoAddrLEA()
395 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
400 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
403 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
416 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
419 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
426 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
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/external/llvm-project/llvm/lib/Target/X86/
DX86FixupLEAs.cpp383 Register DestReg = MI.getOperand(0).getReg(); in optTwoAddrLEA() local
388 if (UseLEAForSP && (DestReg == X86::ESP || DestReg == X86::RSP)) in optTwoAddrLEA()
404 (DestReg == BaseReg || DestReg == IndexReg)) { in optTwoAddrLEA()
406 if (DestReg != BaseReg) in optTwoAddrLEA()
411 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
416 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
419 } else if (DestReg == BaseReg && IndexReg == 0) { in optTwoAddrLEA()
432 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
435 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
442 NewMI = BuildMI(MBB, I, MI.getDebugLoc(), TII->get(NewOpcode), DestReg) in optTwoAddrLEA()
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/external/llvm/lib/Target/Hexagon/
DHexagonSplitConst32AndConst64.cpp93 int DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
96 BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::LO), DestReg) in runOnMachineFunction()
98 BuildMI(*MBB, MII, MI.getDebugLoc(), TII->get(Hexagon::HI), DestReg) in runOnMachineFunction()
108 int DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
121 DestReg) in runOnMachineFunction()
128 int DestReg = MI.getOperand(0).getReg(); in runOnMachineFunction() local
140 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg); in runOnMachineFunction()
141 unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg); in runOnMachineFunction()
/external/llvm-project/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp307 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
321 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
322 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
324 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
329 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
330 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
332 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
334 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
342 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
345 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp307 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
321 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
322 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
324 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
329 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
330 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
332 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
334 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
342 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
345 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
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/external/llvm/lib/Target/Sparc/
DSparcInstrInfo.cpp304 const DebugLoc &DL, unsigned DestReg, in copyPhysReg() argument
318 if (SP::IntRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
319 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0) in copyPhysReg()
321 else if (SP::IntPairRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
326 } else if (SP::FPRegsRegClass.contains(DestReg, SrcReg)) in copyPhysReg()
327 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg) in copyPhysReg()
329 else if (SP::DFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
331 BuildMI(MBB, I, DL, get(SP::FMOVD), DestReg) in copyPhysReg()
339 } else if (SP::QFPRegsRegClass.contains(DestReg, SrcReg)) { in copyPhysReg()
342 BuildMI(MBB, I, DL, get(SP::FMOVQ), DestReg) in copyPhysReg()
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/external/llvm/lib/Target/Mips/
DMipsSEInstrInfo.cpp81 const DebugLoc &DL, unsigned DestReg, in copyPhysReg() argument
86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
115 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
117 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
119 else if (Mips::HI32RegClass.contains(DestReg)) in copyPhysReg()
120 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
121 else if (Mips::LO32RegClass.contains(DestReg)) in copyPhysReg()
122 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
123 else if (Mips::HI32DSPRegClass.contains(DestReg)) in copyPhysReg()
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DMipsFastISel.cpp132 bool emitCmp(unsigned DestReg, const CmpInst *CI);
140 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
143 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
145 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
147 unsigned DestReg);
149 unsigned DestReg);
348 unsigned DestReg = createResultReg(RC); in materializeFP() local
350 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
351 return DestReg; in materializeFP()
354 unsigned DestReg = createResultReg(RC); in materializeFP() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/
DRISCVExpandPseudoInsts.cpp238 Register DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion() local
250 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg) in doAtomicBinOpExpansion()
257 .addReg(DestReg) in doAtomicBinOpExpansion()
274 MachineBasicBlock *MBB, Register DestReg, in insertMaskedMerge() argument
290 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
300 Register DestReg = MI.getOperand(0).getReg(); in doMaskedAtomicBinOpExpansion() local
316 BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg) in doMaskedAtomicBinOpExpansion()
328 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
333 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
338 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
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/external/llvm-project/llvm/lib/Target/RISCV/
DRISCVExpandAtomicPseudoInsts.cpp221 Register DestReg = MI.getOperand(0).getReg(); in doAtomicBinOpExpansion() local
233 BuildMI(LoopMBB, DL, TII->get(getLRForRMW(Ordering, Width)), DestReg) in doAtomicBinOpExpansion()
240 .addReg(DestReg) in doAtomicBinOpExpansion()
257 MachineBasicBlock *MBB, Register DestReg, in insertMaskedMerge() argument
273 BuildMI(MBB, DL, TII->get(RISCV::XOR), DestReg) in insertMaskedMerge()
283 Register DestReg = MI.getOperand(0).getReg(); in doMaskedAtomicBinOpExpansion() local
299 BuildMI(LoopMBB, DL, TII->get(getLRForRMW32(Ordering)), DestReg) in doMaskedAtomicBinOpExpansion()
311 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
316 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
321 .addReg(DestReg) in doMaskedAtomicBinOpExpansion()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsFastISel.cpp180 bool emitCmp(unsigned DestReg, const CmpInst *CI);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
195 unsigned DestReg);
197 unsigned DestReg);
395 unsigned DestReg = createResultReg(RC); in materializeFP() local
397 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
398 return DestReg; in materializeFP()
401 unsigned DestReg = createResultReg(RC); in materializeFP() local
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DMipsSEInstrInfo.cpp85 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
119 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
121 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
123 else if (Mips::HI32RegClass.contains(DestReg)) in copyPhysReg()
124 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
125 else if (Mips::LO32RegClass.contains(DestReg)) in copyPhysReg()
126 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
127 else if (Mips::HI32DSPRegClass.contains(DestReg)) in copyPhysReg()
[all …]
/external/llvm-project/llvm/lib/Target/Mips/
DMipsFastISel.cpp180 bool emitCmp(unsigned DestReg, const CmpInst *CI);
188 bool emitIntExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg,
191 bool emitIntZExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
193 bool emitIntSExt(MVT SrcVT, unsigned SrcReg, MVT DestVT, unsigned DestReg);
195 unsigned DestReg);
197 unsigned DestReg);
395 unsigned DestReg = createResultReg(RC); in materializeFP() local
397 emitInst(Mips::MTC1, DestReg).addReg(TempReg); in materializeFP()
398 return DestReg; in materializeFP()
401 unsigned DestReg = createResultReg(RC); in materializeFP() local
[all …]
DMipsSEInstrInfo.cpp85 const DebugLoc &DL, MCRegister DestReg, in copyPhysReg() argument
90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. in copyPhysReg()
111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) in copyPhysReg()
119 if (Mips::CCRRegClass.contains(DestReg)) in copyPhysReg()
121 else if (Mips::FGR32RegClass.contains(DestReg)) in copyPhysReg()
123 else if (Mips::HI32RegClass.contains(DestReg)) in copyPhysReg()
124 Opc = Mips::MTHI, DestReg = 0; in copyPhysReg()
125 else if (Mips::LO32RegClass.contains(DestReg)) in copyPhysReg()
126 Opc = Mips::MTLO, DestReg = 0; in copyPhysReg()
127 else if (Mips::HI32DSPRegClass.contains(DestReg)) in copyPhysReg()
[all …]

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