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Searched refs:st1w (Results 1 – 25 of 62) sorted by relevance

123

/external/llvm-project/llvm/test/MC/AArch64/SVE/
Dst1w-diagnostics.s6 st1w z19.s, p2, [x18, #-9, MUL VL] label
12 st1w z1.s, p5, [x23, #8, MUL VL] label
18 st1w z21.d, p2, [x29, #-9, MUL VL] label
24 st1w z10.d, p5, [x26, #8, MUL VL] label
32 st1w z1.s, p8, [x3, #1, MUL VL] label
37 st1w z12.d, p8, [x26, #3, MUL VL] label
42 st1w z12.d, p7.b, [x26, #3, MUL VL] label
47 st1w z12.d, p7.q, [x26, #3, MUL VL] label
55 st1w { }, p0, [x0] label
60 st1w { z1.s, z2.s }, p0, [x0] label
[all …]
Dst1w.s10 st1w z0.s, p0, [x0] label
16 st1w z0.d, p0, [x0] label
22 st1w { z0.s }, p0, [x0] label
28 st1w { z0.d }, p0, [x0] label
34 st1w { z31.s }, p7, [sp, #-1, mul vl] label
40 st1w { z21.s }, p5, [x10, #5, mul vl] label
46 st1w { z31.d }, p7, [sp, #-1, mul vl] label
52 st1w { z21.d }, p5, [x10, #5, mul vl] label
58 st1w { z0.s }, p0, [x0, x0, lsl #2] label
64 st1w { z0.d }, p0, [x0, x0, lsl #2] label
[all …]
/external/llvm-project/llvm/test/CodeGen/AArch64/
Dsve-fixed-length-stores.ll49 ; CHECK: st1w { z{{[0-9]+}}.s }, [[PG]], [x0]
58 ; CHECK-DAG: st1w { z{{[0-9]+}}.s }, [[PG]], [x0]
60 ; VBITS_LE_256-DAG: st1w { z{{[0-9]+}}.s }, [[PG]], [x[[A1]]]
69 ; CHECK-DAG: st1w { z{{[0-9]+}}.s }, [[PG]], [x0]
71 ; VBITS_LE_512-DAG: st1w { z{{[0-9]+}}.s }, [[PG]], [x[[A1]]]
73 ; VBITS_LE_256-DAG: st1w { z{{[0-9]+}}.s }, [[PG]], [x[[A2]]]
75 ; VBITS_LE_256-DAG: st1w { z{{[0-9]+}}.s }, [[PG]], [x[[A3]]]
84 ; CHECK-DAG: st1w { z{{[0-9]+}}.s }, [[PG]], [x0]
86 ; VBITS_LE_1024-DAG: st1w { z{{[0-9]+}}.s }, [[PG]], [x[[A1]]]
88 ; VBITS_LE_512-DAG: st1w { z{{[0-9]+}}.s }, [[PG]], [x[[A2]]]
[all …]
Dsve-masked-scatter-legalise.ll30 ; CHECK-DAG: st1w { z0.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, uxtw #2]
31 ; CHECK-DAG: st1w { z1.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, uxtw #2]
42 ; CHECK-DAG: st1w { z0.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2]
43 ; CHECK-DAG: st1w { z1.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2]
44 ; CHECK-DAG: st1w { z2.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2]
45 ; CHECK-DAG: st1w { z3.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2]
46 ; CHECK-DAG: st1w { z4.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2]
47 ; CHECK-DAG: st1w { z5.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2]
48 ; CHECK-DAG: st1w { z6.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2]
49 ; CHECK-DAG: st1w { z7.s }, {{p[0-9]+}}, [x0, {{z[0-9]+}}.s, sxtw #2]
Dsve-split-store.ll35 ; CHECK-NEXT: st1w { z3.s }, p0, [x0, #3, mul vl]
36 ; CHECK-NEXT: st1w { z2.s }, p0, [x0, #2, mul vl]
37 ; CHECK-NEXT: st1w { z1.s }, p0, [x0, #1, mul vl]
38 ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
105 ; CHECK-NEXT: st1w { z1.s }, p2, [x0, #1, mul vl]
106 ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
Dsve-fixed-length-subvector.ll39 ; CHECK: st1w { [[DATA]] }, [[PG]], [x1]
53 ; VBITS_GE_512: st1w { [[DATA]] }, [[PG]], [x1]
67 ; VBITS_GE_1024: st1w { [[DATA]] }, [[PG]], [x1]
81 ; VBITS_GE_2048: st1w { [[DATA]] }, [[PG]], [x1]
118 ; CHECK-NEXT: st1w { [[OR]].s }, [[PG]], [x1]
Dsve-fixed-length-int-extends.ll37 ; CHECK-NEXT: st1w { [[A_WORDS]].s }, [[PG]], [x0]
132 ; CHECK-NEXT: st1w { [[A_HALFS]].s }, [[PG]], [x0]
144 ; VBITS_GE_512-NEXT: st1w { [[A_WORDS]].s }, [[PG]], [x0]
155 ; VBITS_EQ_256-DAG: st1w { [[A_WORDS_LO]].s }, [[PG]], [x0]
156 ; VBITS_EQ_256-DAG: st1w { [[A_WORDS_HI]].s }, [[PG]], [x[[OUT_HI]]]
169 ; VBITS_GE_1024-NEXT: st1w { [[A_WORDS]].s }, [[PG]], [x1]
184 ; VBITS_GE_2048-NEXT: st1w { [[A_WORDS]].s }, [[PG]], [x1]
263 ; CHECK-NEXT: st1w { [[A_WORDS]].s }, [[PG]], [x0]
275 ; VBITS_GE_512-NEXT: st1w { [[A_WORDS]].s }, [[PG]], [x1]
289 ; VBITS_GE_1024-NEXT: st1w { [[A_WORDS]].s }, [[PG]], [x1]
[all …]
Dsve-split-extract-elt.ll87 ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
88 ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
183 ; CHECK-NEXT: st1w { z3.s }, p0, [x8, #3, mul vl]
184 ; CHECK-NEXT: st1w { z2.s }, p0, [x8, #2, mul vl]
185 ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
186 ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
Dsve-fixed-length-fp-rounding.ll131 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
144 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
154 ; VBITS_EQ_256-DAG: st1w { [[RES_LO]].s }, [[PG]], [x0]
155 ; VBITS_EQ_256-DAG: st1w { [[RES_HI]].s }, [[PG]], [x[[A_HI]]
168 ; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
181 ; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
378 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
391 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
401 ; VBITS_EQ_256-DAG: st1w { [[RES_LO]].s }, [[PG]], [x0]
402 ; VBITS_EQ_256-DAG: st1w { [[RES_HI]].s }, [[PG]], [x[[A_HI]]
[all …]
Dsve-intrinsics-scatter-stores-32bit-scaled-offsets.ll65 ; CHECK: st1w { z0.s }, p0, [x0, z1.s, uxtw #2]
76 ; CHECK: st1w { z0.s }, p0, [x0, z1.s, sxtw #2]
87 ; CHECK: st1w { z0.d }, p0, [x0, z1.d, uxtw #2]
99 ; CHECK: st1w { z0.d }, p0, [x0, z1.d, sxtw #2]
111 ; CHECK: st1w { z0.s }, p0, [x0, z1.s, uxtw #2]
122 ; CHECK: st1w { z0.s }, p0, [x0, z1.s, sxtw #2]
Dsve-fixed-length-splat-vector.ll203 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x1]
215 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x1]
222 ; VBITS_EQ_256-DAG: st1w { [[RES]].s }, [[PG]], [x1]
223 ; VBITS_EQ_256-DAG: st1w { [[RES]].s }, [[PG]], [x[[B_HI]]
235 ; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x1]
247 ; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x1]
435 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
447 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
454 ; VBITS_EQ_256-DAG: st1w { [[RES]].s }, [[PG]], [x0]
455 ; VBITS_EQ_256-DAG: st1w { [[RES]].s }, [[PG]], [x[[B_HI]]
[all …]
Dsve-st1-addressing-mode-reg-imm.ll88 ; CHECK-NEXT: st1w { z0.s }, p0, [x0, #2, mul vl]
116 ; CHECK-NEXT: st1w { z0.d }, p0, [x0]
144 ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
147 ; CHECK-NEXT: st1w { z0.d }, p0, [x0, #2, mul vl]
Dsve-intrinsics-scatter-stores-vector-base-imm-offset.ll65 ; CHECK: st1w { z0.s }, p0, [z1.s, #16]
76 ; CHECK: st1w { z0.d }, p0, [z1.d, #16]
88 ; CHECK: st1w { z0.s }, p0, [z1.s, #16]
183 ; CHECK-NEXT: st1w { z0.s }, p0, [x8, z1.s, uxtw]
195 ; CHECK-NEXT: st1w { z0.d }, p0, [x8, z1.d]
208 ; CHECK-NEXT: st1w { z0.s }, p0, [x8, z1.s, uxtw]
Dsve-intrinsics-scatter-stores-32bit-unscaled-offsets.ll114 ; CHECK: st1w { z0.s }, p0, [x0, z1.s, uxtw]
125 ; CHECK: st1w { z0.s }, p0, [x0, z1.s, sxtw]
136 ; CHECK: st1w { z0.d }, p0, [x0, z1.d, uxtw]
148 ; CHECK: st1w { z0.d }, p0, [x0, z1.d, sxtw]
160 ; CHECK: st1w { z0.s }, p0, [x0, z1.s, uxtw]
171 ; CHECK: st1w { z0.s }, p0, [x0, z1.s, sxtw]
Dsve-masked-scatter-32b-scaled.ll22 ; CHECK-NEXT: st1w { z0.d }, p0, [x0, z1.d, sxtw #2]
66 ; CHECK-NEXT: st1w { z0.d }, p0, [x0, z1.d, sxtw #2]
99 ; CHECK-NEXT: st1w { z0.d }, p0, [x0, z1.d, uxtw #2]
143 ; CHECK-NEXT: st1w { z0.d }, p0, [x0, z1.d, uxtw #2]
180 ; CHECK-NEXT: st1w { z0.s }, p0, [x0, z1.s, sxtw #2]
213 ; CHECK-NEXT: st1w { z0.s }, p0, [x0, z1.s, sxtw #2]
235 ; CHECK-NEXT: st1w { z0.s }, p0, [x0, z1.s, uxtw #2]
268 ; CHECK-NEXT: st1w { z0.s }, p0, [x0, z1.s, uxtw #2]
Dsve-fixed-length-fp-arith.ll160 ; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
177 ; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
194 ; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
211 ; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
415 ; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
430 ; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
445 ; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
460 ; CHECK: st1w { [[RES]].s }, [[PG]], [x0]
662 ; CHECK: st1w { [[OP3]].s }, [[PG]], [x0]
679 ; CHECK: st1w { [[OP3]].s }, [[PG]], [x0]
[all …]
Dsve-fixed-length-fp-minmax.ll143 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
158 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
171 ; VBITS_EQ_256-DAG: st1w { [[RES_LO]].s }, [[PG]], [x0]
172 ; VBITS_EQ_256-DAG: st1w { [[RES_HI]].s }, [[PG]], [x[[A_HI]]
187 ; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
202 ; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
423 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
438 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
451 ; VBITS_EQ_256-DAG: st1w { [[RES_LO]].s }, [[PG]], [x0]
452 ; VBITS_EQ_256-DAG: st1w { [[RES_HI]].s }, [[PG]], [x[[A_HI]]
[all …]
Dsve-split-insert-elt.ll61 ; CHECK-NEXT: st1w { z1.s }, p0, [x9, #1, mul vl]
62 ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
180 ; CHECK-NEXT: st1w { z1.s }, p0, [x8, #1, mul vl]
181 ; CHECK-NEXT: st1w { z0.s }, p0, [sp]
Dsve-redundant-store.ll24 ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
Dsve-masked-scatter-64b-scaled.ll21 ; CHECK-NEXT: st1w { z0.d }, p0, [x0, z1.d, lsl #2]
51 ; CHECK-NEXT: st1w { z0.d }, p0, [x0, z1.d, lsl #2]
Dsve-intrinsics-scatter-stores-vector-base-scalar-offset.ll65 ; CHECK: st1w { z0.s }, p0, [x0, z1.s, uxtw]
76 ; CHECK: st1w { z0.d }, p0, [x0, z1.d]
88 ; CHECK: st1w { z0.s }, p0, [x0, z1.s, uxtw]
Dsve-masked-scatter-32b-unscaled.ll35 ; CHECK-NEXT: st1w { z0.d }, p0, [x0, z1.d, sxtw]
83 ; CHECK-NEXT: st1w { z0.d }, p0, [x0, z1.d, sxtw]
131 ; CHECK-NEXT: st1w { z0.d }, p0, [x0, z1.d, uxtw]
179 ; CHECK-NEXT: st1w { z0.d }, p0, [x0, z1.d, uxtw]
230 ; CHECK-NEXT: st1w { z0.s }, p0, [x0, z1.s, sxtw]
266 ; CHECK-NEXT: st1w { z0.s }, p0, [x0, z1.s, sxtw]
302 ; CHECK-NEXT: st1w { z0.s }, p0, [x0, z1.s, uxtw]
338 ; CHECK-NEXT: st1w { z0.s }, p0, [x0, z1.s, uxtw]
Dsve-fixed-length-int-immediates.ll55 ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
124 ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
192 ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
265 ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
336 ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
407 ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
476 ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
544 ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
615 ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
687 ; CHECK-NEXT: st1w { z0.s }, p0, [x0]
[all …]
Dsve-fixed-length-int-shifts.ll240 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
255 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
268 ; VBITS_EQ_256-DAG: st1w { [[RES_LO]].s }, [[PG]], [x0]
269 ; VBITS_EQ_256-DAG: st1w { [[RES_HI]].s }, [[PG]], [x[[A_HI]]
284 ; VBITS_GE_1024-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
299 ; VBITS_GE_2048-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
619 ; CHECK-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
634 ; VBITS_GE_512-NEXT: st1w { [[RES]].s }, [[PG]], [x0]
647 ; VBITS_EQ_256-DAG: st1w { [[RES_LO]].s }, [[PG]], [x0]
648 ; VBITS_EQ_256-DAG: st1w { [[RES_HI]].s }, [[PG]], [x[[A_HI]]
[all …]
Dsve-intrinsics-st1.ll117 ; CHECK: st1w { z0.s }, p0, [x0]
127 ; CHECK: st1w { z0.s }, p0, [x0]
137 ; CHECK: st1w { z0.d }, p0, [x0]

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