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Searched refs:Reg (Results 1 – 25 of 197) sorted by relevance

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/external/qemu/target-i386/
Dops_sse_header.h21 #define Reg MMXReg macro
24 #define Reg XMMReg macro
31 #define dh_ctype_Reg Reg *
38 DEF_HELPER_2(glue(psrlw, SUFFIX), void, Reg, Reg)
39 DEF_HELPER_2(glue(psraw, SUFFIX), void, Reg, Reg)
40 DEF_HELPER_2(glue(psllw, SUFFIX), void, Reg, Reg)
41 DEF_HELPER_2(glue(psrld, SUFFIX), void, Reg, Reg)
42 DEF_HELPER_2(glue(psrad, SUFFIX), void, Reg, Reg)
43 DEF_HELPER_2(glue(pslld, SUFFIX), void, Reg, Reg)
44 DEF_HELPER_2(glue(psrlq, SUFFIX), void, Reg, Reg)
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Dops_sse.h22 #define Reg MMXReg macro
30 #define Reg XMMReg macro
39 void glue(helper_psrlw, SUFFIX)(Reg *d, Reg *s) in glue()
63 void glue(helper_psraw, SUFFIX)(Reg *d, Reg *s) in glue()
84 void glue(helper_psllw, SUFFIX)(Reg *d, Reg *s) in glue()
108 void glue(helper_psrld, SUFFIX)(Reg *d, Reg *s) in glue()
128 void glue(helper_psrad, SUFFIX)(Reg *d, Reg *s) in glue()
145 void glue(helper_pslld, SUFFIX)(Reg *d, Reg *s) in glue()
165 void glue(helper_psrlq, SUFFIX)(Reg *d, Reg *s) in glue()
183 void glue(helper_psllq, SUFFIX)(Reg *d, Reg *s) in glue()
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/external/llvm/lib/CodeGen/
DCriticalAntiDepBreaker.cpp64 unsigned Reg = *I; in StartBlock() local
65 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
66 KillIndices[Reg] = BB->size(); in StartBlock()
67 DefIndices[Reg] = ~0u; in StartBlock()
70 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { in StartBlock()
86 unsigned Reg = *I; in StartBlock() local
87 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1); in StartBlock()
88 KillIndices[Reg] = BB->size(); in StartBlock()
89 DefIndices[Reg] = ~0u; in StartBlock()
92 for (const unsigned *Alias = TRI->getAliasSet(Reg); *Alias; ++Alias) { in StartBlock()
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DAggressiveAntiDepBreaker.cpp61 unsigned AggressiveAntiDepState::GetGroup(unsigned Reg) { in GetGroup() argument
62 unsigned Node = GroupNodeIndices[Reg]; in GetGroup()
74 for (unsigned Reg = 0; Reg != NumTargetRegs; ++Reg) { in GetGroupRegs() local
75 if ((GetGroup(Reg) == Group) && (RegRefs->count(Reg) > 0)) in GetGroupRegs()
76 Regs.push_back(Reg); in GetGroupRegs()
96 unsigned AggressiveAntiDepState::LeaveGroup(unsigned Reg) in LeaveGroup() argument
103 GroupNodeIndices[Reg] = idx; in LeaveGroup()
107 bool AggressiveAntiDepState::IsLive(unsigned Reg) in IsLive() argument
111 return((KillIndices[Reg] != ~0u) && (DefIndices[Reg] == ~0u)); in IsLive()
161 unsigned Reg = *Alias; ++Alias) { in StartBlock()
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DMachineRegisterInfo.cpp45 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) { in setRegClass() argument
46 VRegInfo[Reg].first = RC; in setRegClass()
50 MachineRegisterInfo::constrainRegClass(unsigned Reg, in constrainRegClass() argument
52 const TargetRegisterClass *OldRC = getRegClass(Reg); in constrainRegClass()
59 setRegClass(Reg, NewRC); in constrainRegClass()
73 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs()); in createVirtualRegister() local
78 VRegInfo.grow(Reg); in createVirtualRegister()
79 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
80 RegAllocHints.grow(Reg); in createVirtualRegister()
85 return Reg; in createVirtualRegister()
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DLiveVariables.cpp178 void LiveVariables::HandleVirtRegDef(unsigned Reg, MachineInstr *MI) { in HandleVirtRegDef() argument
179 VarInfo &VRInfo = getVarInfo(Reg); in HandleVirtRegDef()
188 MachineInstr *LiveVariables::FindLastPartialDef(unsigned Reg, in FindLastPartialDef() argument
193 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in FindLastPartialDef()
215 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
228 void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) { in HandlePhysRegUse() argument
229 MachineInstr *LastDef = PhysRegDef[Reg]; in HandlePhysRegUse()
231 if (!LastDef && !PhysRegUse[Reg]) { in HandlePhysRegUse()
241 MachineInstr *LastPartialDef = FindLastPartialDef(Reg, PartDefRegs); in HandlePhysRegUse()
244 LastPartialDef->addOperand(MachineOperand::CreateReg(Reg, true/*IsDef*/, in HandlePhysRegUse()
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DProcessImplicitDefs.cpp49 unsigned Reg, unsigned OpIdx, in CanTurnIntoImplicitDef() argument
62 static bool isUndefCopy(MachineInstr *MI, unsigned Reg, in isUndefCopy() argument
67 if (MO1.getReg() != Reg) in isUndefCopy()
110 unsigned Reg = MI->getOperand(0).getReg(); in runOnMachineFunction() local
111 ImpDefRegs.insert(Reg); in runOnMachineFunction()
112 if (TargetRegisterInfo::isPhysicalRegister(Reg)) { in runOnMachineFunction()
113 for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS) in runOnMachineFunction()
139 unsigned Reg = MO.getReg(); in runOnMachineFunction() local
140 if (!Reg) in runOnMachineFunction()
142 if (!ImpDefRegs.count(Reg)) in runOnMachineFunction()
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DRegisterScavenging.cpp37 void RegScavenger::setUsed(unsigned Reg) { in setUsed() argument
38 RegsAvailable.reset(Reg); in setUsed()
40 for (const unsigned *SubRegs = TRI->getSubRegisters(Reg); in setUsed()
45 bool RegScavenger::isAliasUsed(unsigned Reg) const { in isAliasUsed()
46 if (isUsed(Reg)) in isAliasUsed()
48 for (const unsigned *R = TRI->getAliasSet(Reg); *R; ++R) in isAliasUsed()
111 void RegScavenger::addRegWithSubRegs(BitVector &BV, unsigned Reg) { in addRegWithSubRegs() argument
112 BV.set(Reg); in addRegWithSubRegs()
113 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++) in addRegWithSubRegs()
117 void RegScavenger::addRegWithAliases(BitVector &BV, unsigned Reg) { in addRegWithAliases() argument
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DDeadMachineInstructionElim.cpp72 unsigned Reg = MO.getReg(); in isDead() local
73 if (TargetRegisterInfo::isPhysicalRegister(Reg) ? in isDead()
74 LivePhysRegs[Reg] : !MRI->use_nodbg_empty(Reg)) { in isDead()
108 unsigned Reg = *LOI; in runOnMachineFunction() local
109 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in runOnMachineFunction()
110 LivePhysRegs.set(Reg); in runOnMachineFunction()
138 unsigned Reg = MO.getReg(); in runOnMachineFunction() local
139 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in runOnMachineFunction()
142 for (MachineRegisterInfo::use_iterator I = MRI->use_begin(Reg), in runOnMachineFunction()
166 unsigned Reg = MO.getReg(); in runOnMachineFunction() local
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DInlineSpiller.cpp94 SibValueInfo(unsigned Reg, VNInfo *VNI) in SibValueInfo()
95 : AllDefsAreReloads(false), SpillReg(Reg), SpillVNI(VNI), DefMI(0) {} in SibValueInfo()
130 bool isRegToSpill(unsigned Reg) { in isRegToSpill() argument
132 RegsToSpill.end(), Reg) != RegsToSpill.end(); in isRegToSpill()
135 bool isSibling(unsigned Reg);
146 bool coalesceStackAccess(MachineInstr *MI, unsigned Reg);
155 void spillAroundUses(unsigned Reg);
182 static unsigned isFullCopyOf(const MachineInstr *MI, unsigned Reg) { in isFullCopyOf() argument
185 if (MI->getOperand(0).getReg() == Reg) in isFullCopyOf()
187 if (MI->getOperand(1).getReg() == Reg) in isFullCopyOf()
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DMachineLICM.cpp157 void AddToLiveIns(unsigned Reg);
173 bool HasAnyPHIUse(unsigned Reg) const;
179 unsigned Reg) const;
375 unsigned Reg = MO.getReg(); in ProcessMI() local
376 if (!Reg) in ProcessMI()
378 assert(TargetRegisterInfo::isPhysicalRegister(Reg) && in ProcessMI()
382 if (Reg && PhysRegDefs[Reg]) in ProcessMI()
390 ++PhysRegDefs[Reg]; in ProcessMI()
391 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) in ProcessMI()
406 Def = Reg; in ProcessMI()
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DRegAllocFast.cpp656 unsigned Reg = MO.getReg(); in handleThroughOperands() local
657 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in handleThroughOperands()
660 (MO.getSubReg() && MI->readsVirtualRegister(Reg))) { in handleThroughOperands()
661 if (ThroughRegs.insert(Reg)) in handleThroughOperands()
662 DEBUG(dbgs() << ' ' << PrintReg(Reg)); in handleThroughOperands()
672 unsigned Reg = MO.getReg(); in handleThroughOperands() local
673 if (!Reg || !TargetRegisterInfo::isPhysicalRegister(Reg)) continue; in handleThroughOperands()
674 UsedInInstr.set(Reg); in handleThroughOperands()
675 if (ThroughRegs.count(PhysRegState[Reg])) in handleThroughOperands()
676 definePhysReg(MI, Reg, regFree); in handleThroughOperands()
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DVirtRegMap.cpp233 unsigned Reg = TargetRegisterInfo::index2VirtReg(i); in FindUnusedRegisters() local
234 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) in FindUnusedRegisters()
235 Used.set(Virt2PhysMap[Reg]); in FindUnusedRegisters()
240 for (unsigned Reg = 1; Reg < NumRegs; ++Reg) { in FindUnusedRegisters() local
241 if (Allocatable[Reg] && !Used[Reg] && !LIs->hasInterval(Reg)) { in FindUnusedRegisters()
243 for (const unsigned *AS = TRI->getAliasSet(Reg); *AS; ++AS) { in FindUnusedRegisters()
251 UnusedRegs.set(Reg); in FindUnusedRegisters()
340 for (unsigned Reg = 1, RegE = TRI->getNumRegs(); Reg != RegE; ++Reg) in rewrite() local
341 if (!MRI->reg_nodbg_empty(Reg)) in rewrite()
342 MRI->setPhysRegUsed(Reg); in rewrite()
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DMachineSink.cpp90 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
142 MachineSinking::AllUsesDominatedByBlock(unsigned Reg, in AllUsesDominatedByBlock() argument
147 assert(TargetRegisterInfo::isVirtualRegister(Reg) && in AllUsesDominatedByBlock()
150 if (MRI->use_nodbg_empty(Reg)) in AllUsesDominatedByBlock()
175 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); in AllUsesDominatedByBlock()
189 I = MRI->use_nodbg_begin(Reg), E = MRI->use_nodbg_end(); in AllUsesDominatedByBlock()
303 unsigned Reg = MO.getReg(); in isWorthBreakingCriticalEdge() local
304 if (Reg == 0 || !TargetRegisterInfo::isPhysicalRegister(Reg)) in isWorthBreakingCriticalEdge()
306 if (MRI->hasOneNonDBGUse(Reg)) in isWorthBreakingCriticalEdge()
418 unsigned Reg = MO.getReg(); in SinkInstruction() local
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DRegAllocLinearScan.cpp257 void DowngradeRegister(LiveInterval *li, unsigned Reg);
260 void UpgradeRegister(unsigned Reg);
286 unsigned attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg);
448 unsigned RALinScan::attemptTrivialCoalescing(LiveInterval &cur, unsigned Reg) { in attemptTrivialCoalescing() argument
450 if ((Preference && Preference == Reg) || !cur.containsOneValue()) in attemptTrivialCoalescing()
451 return Reg; in attemptTrivialCoalescing()
455 return Reg; in attemptTrivialCoalescing()
461 return Reg; in attemptTrivialCoalescing()
475 return Reg; in attemptTrivialCoalescing()
479 return Reg; in attemptTrivialCoalescing()
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DMachineInstr.cpp58 Contents.Reg.Prev = 0; in AddRegOperandToRegInfo()
59 Contents.Reg.Next = 0; in AddRegOperandToRegInfo()
70 Head = &(*Head)->Contents.Reg.Next; in AddRegOperandToRegInfo()
72 Contents.Reg.Next = *Head; in AddRegOperandToRegInfo()
73 if (Contents.Reg.Next) { in AddRegOperandToRegInfo()
74 assert(getReg() == Contents.Reg.Next->getReg() && in AddRegOperandToRegInfo()
76 Contents.Reg.Next->Contents.Reg.Prev = &Contents.Reg.Next; in AddRegOperandToRegInfo()
79 Contents.Reg.Prev = Head; in AddRegOperandToRegInfo()
88 MachineOperand *NextOp = Contents.Reg.Next; in RemoveRegOperandFromRegInfo()
89 *Contents.Reg.Prev = NextOp; in RemoveRegOperandFromRegInfo()
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DMachineVerifier.cpp83 void addRegWithSubRegs(RegVector &RV, unsigned Reg) { in addRegWithSubRegs()
84 RV.push_back(Reg); in addRegWithSubRegs()
85 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in addRegWithSubRegs()
86 for (const unsigned *R = TRI->getSubRegisters(Reg); *R; R++) in addRegWithSubRegs()
118 bool addPassed(unsigned Reg) { in addPassed()
119 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in addPassed()
121 if (regsKilled.count(Reg) || regsLiveOut.count(Reg)) in addPassed()
123 return vregsPassed.insert(Reg).second; in addPassed()
137 bool addRequired(unsigned Reg) { in addRequired()
138 if (!TargetRegisterInfo::isVirtualRegister(Reg)) in addRequired()
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/external/llvm/include/llvm/CodeGen/
DMachineRegisterInfo.h171 MachineInstr *getVRegDef(unsigned Reg) const;
177 void clearKillFlags(unsigned Reg) const;
189 const TargetRegisterClass *getRegClass(unsigned Reg) const { in getRegClass() argument
190 return VRegInfo[Reg].first; in getRegClass()
195 void setRegClass(unsigned Reg, const TargetRegisterClass *RC);
202 const TargetRegisterClass *constrainRegClass(unsigned Reg,
216 void setRegAllocationHint(unsigned Reg, unsigned Type, unsigned PrefReg) { in setRegAllocationHint() argument
217 RegAllocHints[Reg].first = Type; in setRegAllocationHint()
218 RegAllocHints[Reg].second = PrefReg; in setRegAllocationHint()
224 getRegAllocationHint(unsigned Reg) const { in getRegAllocationHint() argument
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DLiveVariables.h118 unsigned Reg,
167 bool HandlePhysRegKill(unsigned Reg, MachineInstr *MI);
169 void HandlePhysRegUse(unsigned Reg, MachineInstr *MI);
170 void HandlePhysRegDef(unsigned Reg, MachineInstr *MI,
176 MachineInstr *FindLastRefOrPartRef(unsigned Reg);
181 MachineInstr *FindLastPartialDef(unsigned Reg,
195 bool RegisterDefIsDead(MachineInstr *MI, unsigned Reg) const;
202 void replaceKillInstruction(unsigned Reg, MachineInstr *OldMI,
290 bool isLiveIn(unsigned Reg, const MachineBasicBlock &MBB) { in isLiveIn() argument
291 return getVarInfo(Reg).isLiveIn(MBB, Reg, *MRI); in isLiveIn()
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DCallingConvLower.h190 bool isAllocated(unsigned Reg) const { in isAllocated() argument
191 return UsedRegs[Reg/32] & (1 << (Reg&31)); in isAllocated()
242 unsigned AllocateReg(unsigned Reg) { in AllocateReg() argument
243 if (isAllocated(Reg)) return 0; in AllocateReg()
244 MarkAllocated(Reg); in AllocateReg()
245 return Reg; in AllocateReg()
249 unsigned AllocateReg(unsigned Reg, unsigned ShadowReg) { in AllocateReg() argument
250 if (isAllocated(Reg)) return 0; in AllocateReg()
251 MarkAllocated(Reg); in AllocateReg()
253 return Reg; in AllocateReg()
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DRegisterScavenging.h126 void setUsed(unsigned Reg);
129 bool isReserved(unsigned Reg) const { return ReservedRegs.test(Reg); } in isReserved() argument
133 bool isUsed(unsigned Reg) const { return !RegsAvailable.test(Reg); } in isUsed() argument
134 bool isUnused(unsigned Reg) const { return RegsAvailable.test(Reg); } in isUnused() argument
137 bool isAliasUsed(unsigned Reg) const;
149 void addRegWithSubRegs(BitVector &BV, unsigned Reg);
152 void addRegWithAliases(BitVector &BV, unsigned Reg);
DMachineInstr.h312 bool readsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
313 return findRegisterUseOperandIdx(Reg, false, TRI) != -1;
319 bool readsVirtualRegister(unsigned Reg) const {
320 return readsWritesVirtualRegister(Reg).first;
327 std::pair<bool,bool> readsWritesVirtualRegister(unsigned Reg,
333 bool killsRegister(unsigned Reg, const TargetRegisterInfo *TRI = NULL) const {
334 return findRegisterUseOperandIdx(Reg, true, TRI) != -1;
341 bool definesRegister(unsigned Reg, const TargetRegisterInfo *TRI=NULL) const {
342 return findRegisterDefOperandIdx(Reg, false, false, TRI) != -1;
348 bool modifiesRegister(unsigned Reg, const TargetRegisterInfo *TRI) const {
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/external/llvm/include/llvm/Target/
DTargetRegisterInfo.h100 bool contains(unsigned Reg) const { in contains() argument
101 return RegSet.count(Reg); in contains()
306 static bool isStackSlot(unsigned Reg) { in isStackSlot() argument
307 return int(Reg) >= (1 << 30); in isStackSlot()
312 static int stackSlot2Index(unsigned Reg) { in stackSlot2Index() argument
313 assert(isStackSlot(Reg) && "Not a stack slot"); in stackSlot2Index()
314 return int(Reg - (1u << 30)); in stackSlot2Index()
326 static bool isPhysicalRegister(unsigned Reg) { in isPhysicalRegister() argument
327 assert(!isStackSlot(Reg) && "Not a register! Check isStackSlot() first."); in isPhysicalRegister()
328 return int(Reg) > 0; in isPhysicalRegister()
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/external/llvm/lib/Target/ARM/
DMLxExpansionPass.cpp63 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
87 unsigned Reg = MI->getOperand(1).getReg(); in getAccDefMI() local
88 if (TargetRegisterInfo::isPhysicalRegister(Reg)) in getAccDefMI()
92 MachineInstr *DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
97 Reg = DefMI->getOperand(1).getReg(); in getAccDefMI()
98 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in getAccDefMI()
99 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
103 Reg = DefMI->getOperand(2).getReg(); in getAccDefMI()
104 if (TargetRegisterInfo::isVirtualRegister(Reg)) { in getAccDefMI()
105 DefMI = MRI->getVRegDef(Reg); in getAccDefMI()
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DARMBaseRegisterInfo.h38 static inline bool isARMLowRegister(unsigned Reg) { in isARMLowRegister() argument
40 switch (Reg) { in isARMLowRegister()
51 static inline bool isARMArea1Register(unsigned Reg, bool isDarwin) { in isARMArea1Register() argument
53 switch (Reg) { in isARMArea1Register()
66 static inline bool isARMArea2Register(unsigned Reg, bool isDarwin) { in isARMArea2Register() argument
68 switch (Reg) { in isARMArea2Register()
77 static inline bool isARMArea3Register(unsigned Reg, bool isDarwin) { in isARMArea3Register() argument
79 switch (Reg) { in isARMArea3Register()
143 unsigned ResolveRegAllocHint(unsigned Type, unsigned Reg,
146 void UpdateRegAllocHint(unsigned Reg, unsigned NewReg,
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