/arch/x86/power/ |
D | cpu_64.c | 59 rdmsrl(MSR_FS_BASE, ctxt->fs_base); in __save_processor_state() 60 rdmsrl(MSR_GS_BASE, ctxt->gs_base); in __save_processor_state() 61 rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base); in __save_processor_state() 67 rdmsrl(MSR_EFER, ctxt->efer); in __save_processor_state()
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/arch/x86/kernel/ |
D | time_64.c | 86 rdmsrl(MSR_K7_EVNTSEL3, evntsel3); in calibrate_cpu() 88 rdmsrl(MSR_K7_PERFCTR3, pmc3); in calibrate_cpu() 99 rdmsrl(MSR_K7_PERFCTR0 + i, pmc_now); in calibrate_cpu()
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D | mmconf-fam10h_64.c | 101 rdmsrl(address, val); in get_fam10h_pci_mmconf_base() 109 rdmsrl(address, val); in get_fam10h_pci_mmconf_base() 186 rdmsrl(address, val); in fam10h_check_enable_mmcfg()
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D | process_64.c | 188 rdmsrl(MSR_FS_BASE, fs); in __show_regs() 189 rdmsrl(MSR_GS_BASE, gs); in __show_regs() 190 rdmsrl(MSR_KERNEL_GS_BASE, shadowgs); in __show_regs() 807 rdmsrl(MSR_FS_BASE, base); in do_arch_prctl() 821 rdmsrl(MSR_KERNEL_GS_BASE, base); in do_arch_prctl()
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/arch/x86/oprofile/ |
D | op_model_amd.c | 167 rdmsrl(MSR_AMD64_IBSFETCHLINAD, msr); in op_amd_handle_ibs() 174 rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, msr); in op_amd_handle_ibs() 190 rdmsrl(MSR_AMD64_IBSOPRIP, msr); in op_amd_handle_ibs() 195 rdmsrl(MSR_AMD64_IBSOPDATA, msr); in op_amd_handle_ibs() 198 rdmsrl(MSR_AMD64_IBSOPDATA2, msr); in op_amd_handle_ibs() 201 rdmsrl(MSR_AMD64_IBSOPDATA3, msr); in op_amd_handle_ibs() 204 rdmsrl(MSR_AMD64_IBSDCLINAD, msr); in op_amd_handle_ibs() 207 rdmsrl(MSR_AMD64_IBSDCPHYSAD, msr); in op_amd_handle_ibs()
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D | op_model_ppro.c | 142 rdmsrl(msrs->counters[i].addr, val); in ppro_check_ctrs()
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/arch/x86/include/asm/ |
D | virtext.h | 120 rdmsrl(MSR_EFER, efer); in cpu_svm_disable()
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D | msr.h | 147 #define rdmsrl(msr, val) \ macro
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D | processor.h | 767 rdmsrl(MSR_IA32_DEBUGCTLMSR, debugctlmsr); in get_debugctlmsr()
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D | kvm_host.h | 694 rdmsrl(msr, value); in read_msr()
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/arch/x86/kernel/cpu/mcheck/ |
D | mce_64.c | 169 rdmsrl(rip_msr, m->ip); in mce_get_rip() 204 rdmsrl(MSR_IA32_MCG_STATUS, m.mcgstatus); in do_machine_check() 221 rdmsrl(MSR_IA32_MC0_STATUS + i*4, m.status); in do_machine_check() 241 rdmsrl(MSR_IA32_MC0_MISC + i*4, m.misc); in do_machine_check() 243 rdmsrl(MSR_IA32_MC0_ADDR + i*4, m.addr); in do_machine_check() 446 rdmsrl(MSR_IA32_MCG_CAP, cap); in mce_init()
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D | mce_intel_64.c | 25 rdmsrl(MSR_IA32_THERM_STATUS, msr_val); in smp_thermal_interrupt()
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D | p4.c | 53 rdmsrl(MSR_IA32_THERM_STATUS, msr_val); in intel_thermal_interrupt()
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D | mce_amd_64.c | 239 rdmsrl(address, m.misc); in mce_threshold_interrupt() 240 rdmsrl(MSR_IA32_MC0_STATUS + bank * 4, in mce_threshold_interrupt()
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/arch/x86/pci/ |
D | amd_bus.c | 255 rdmsrl(address, msr); in get_pci_mmcfg_amd_fam10h_range() 417 rdmsrl(address, val); in early_fill_mp_bus_info() 506 rdmsrl(address, val); in early_fill_mp_bus_info() 511 rdmsrl(address, val); in early_fill_mp_bus_info() 572 rdmsrl(MSR_AMD64_NB_CFG, reg); in enable_pci_io_ecs()
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/arch/x86/kernel/cpu/cpufreq/ |
D | powernow-k7.c | 217 rdmsrl (MSR_K7_FID_VID_CTL, fidvidctl.val); in change_FID() 232 rdmsrl (MSR_K7_FID_VID_CTL, fidvidctl.val); in change_VID() 260 rdmsrl (MSR_K7_FID_VID_STATUS, fidvidstatus.val); in change_speed() 569 rdmsrl (MSR_K7_FID_VID_STATUS, fidvidstatus.val); in powernow_get() 609 rdmsrl (MSR_K7_FID_VID_STATUS, fidvidstatus.val); in powernow_cpu_init()
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D | e_powersaver.c | 206 rdmsrl(MSR_IA32_MISC_ENABLE, val); in eps_cpu_init() 211 rdmsrl(MSR_IA32_MISC_ENABLE, val); in eps_cpu_init()
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D | longhaul.c | 142 rdmsrl(MSR_VIA_BCR2, bcr2.val); in do_longhaul1() 157 rdmsrl(MSR_VIA_BCR2, bcr2.val); in do_longhaul1() 170 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val); in do_powersaver() 540 rdmsrl(MSR_VIA_LONGHAUL, longhaul.val); in longhaul_setup_voltagescaling()
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/arch/x86/kernel/cpu/ |
D | perfctr-watchdog.c | 621 rdmsrl(wd->cccr_msr, dummy); in p4_rearm() 795 rdmsrl(wd->perfctr_msr, ctr); in lapic_wd_event()
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D | intel.c | 36 rdmsrl(MSR_IA32_MISC_ENABLE, misc_enable); in early_init_intel()
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D | amd.c | 319 rdmsrl(MSR_K7_HWCR, value); in init_amd()
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/arch/x86/kvm/ |
D | vmx.c | 185 rdmsrl(e[i].index, e[i].data); in save_msrs() 674 rdmsrl(MSR_IA32_SYSENTER_ESP, sysenter_esp); in vmx_vcpu_load() 1056 rdmsrl(MSR_IA32_FEATURE_CONTROL, msr); in vmx_disabled_by_bios() 1070 rdmsrl(MSR_IA32_FEATURE_CONTROL, old); in hardware_enable() 2176 rdmsrl(MSR_FS_BASE, a); in vmx_vcpu_setup() 2178 rdmsrl(MSR_GS_BASE, a); in vmx_vcpu_setup() 2198 rdmsrl(MSR_IA32_SYSENTER_ESP, a); in vmx_vcpu_setup() 2200 rdmsrl(MSR_IA32_SYSENTER_EIP, a); in vmx_vcpu_setup()
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D | svm.c | 294 rdmsrl(MSR_EFER, efer); in svm_hardware_enable() 696 rdmsrl(host_save_user_msrs[i], svm->host_user_msrs[i]); in svm_vcpu_load() 933 rdmsrl(MSR_GS_BASE, to_svm(vcpu)->host_gs_base); in save_host_msrs() 1881 rdmsrl(MSR_VM_CR, vm_cr);
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/arch/x86/mm/ |
D | pat.c | 112 rdmsrl(MSR_IA32_CR_PAT, boot_pat_state); in pat_init()
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D | init_64.c | 123 rdmsrl(MSR_EFER, efer); in check_efer()
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