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Searched refs:I915_READ (Results 1 – 25 of 53) sorted by relevance

123

/drivers/gpu/drm/i915/
Di915_suspend.c36 dev_priv->regfile.saveDSPARB = I915_READ(DSPARB); in i915_save_display()
40 dev_priv->regfile.saveFBC_CONTROL = I915_READ(FBC_CONTROL); in i915_save_display()
74 dev_priv->regfile.saveCACHE_MODE_0 = I915_READ(CACHE_MODE_0); in i915_save_state()
77 dev_priv->regfile.saveMI_ARB_STATE = I915_READ(MI_ARB_STATE); in i915_save_state()
82 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); in i915_save_state()
83 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); in i915_save_state()
86 dev_priv->regfile.saveSWF3[i] = I915_READ(SWF3(i)); in i915_save_state()
89 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); in i915_save_state()
92 dev_priv->regfile.saveSWF0[i] = I915_READ(SWF0(i)); in i915_save_state()
93 dev_priv->regfile.saveSWF1[i] = I915_READ(SWF1(i)); in i915_save_state()
[all …]
Di915_debugfs.c683 I915_READ(GEN8_MASTER_IRQ)); in i915_interrupt_info()
686 I915_READ(VLV_IER)); in i915_interrupt_info()
688 I915_READ(VLV_IIR)); in i915_interrupt_info()
690 I915_READ(VLV_IIR_RW)); in i915_interrupt_info()
692 I915_READ(VLV_IMR)); in i915_interrupt_info()
706 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()
713 I915_READ(PORT_HOTPLUG_EN)); in i915_interrupt_info()
715 I915_READ(VLV_DPFLIPSTAT)); in i915_interrupt_info()
717 I915_READ(DPINVGTT)); in i915_interrupt_info()
722 i, I915_READ(GEN8_GT_IMR(i))); in i915_interrupt_info()
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Dintel_dsi.c111 u32 val = I915_READ(reg); in read_data()
265 if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) in dpi_send_cmd()
362 tmp = I915_READ(MIPI_CTRL(port)); in glk_dsi_enable_io()
367 tmp = I915_READ(MIPI_CTRL(PORT_A)); in glk_dsi_enable_io()
373 tmp = I915_READ(MIPI_CTRL(port)); in glk_dsi_enable_io()
374 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) in glk_dsi_enable_io()
391 cold_boot |= !(I915_READ(MIPI_DEVICE_READY(port)) & in glk_dsi_enable_io()
414 val = I915_READ(MIPI_CTRL(PORT_A)); in glk_dsi_device_ready()
419 if (!(I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY)) { in glk_dsi_device_ready()
420 val = I915_READ(MIPI_DEVICE_READY(port)); in glk_dsi_device_ready()
[all …]
Dintel_dpll_mgr.c349 val = I915_READ(PCH_DPLL(pll->id)); in ibx_pch_dpll_get_hw_state()
351 hw_state->fp0 = I915_READ(PCH_FP0(pll->id)); in ibx_pch_dpll_get_hw_state()
352 hw_state->fp1 = I915_READ(PCH_FP1(pll->id)); in ibx_pch_dpll_get_hw_state()
373 val = I915_READ(PCH_DREF_CONTROL); in ibx_assert_pch_refclk_enabled()
487 val = I915_READ(WRPLL_CTL(pll->id)); in hsw_ddi_wrpll_disable()
497 val = I915_READ(SPLL_CTL); in hsw_ddi_spll_disable()
511 val = I915_READ(WRPLL_CTL(pll->id)); in hsw_ddi_wrpll_get_hw_state()
528 val = I915_READ(SPLL_CTL); in hsw_ddi_spll_get_hw_state()
923 val = I915_READ(DPLL_CTRL1); in skl_ddi_pll_write_ctrl1()
947 I915_READ(regs[pll->id].ctl) | LCPLL_PLL_ENABLE); in skl_ddi_pll_enable()
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Dintel_audio.c223 tmp = I915_READ(reg_eldv); in intel_eld_uptodate()
229 tmp = I915_READ(reg_elda); in intel_eld_uptodate()
234 if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) in intel_eld_uptodate()
247 tmp = I915_READ(G4X_AUD_VID_DID); in g4x_audio_codec_disable()
254 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_disable()
271 tmp = I915_READ(G4X_AUD_VID_DID); in g4x_audio_codec_enable()
283 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
293 tmp = I915_READ(G4X_AUD_CNTL_ST); in g4x_audio_codec_enable()
314 tmp = I915_READ(HSW_AUD_CFG(pipe)); in hsw_dp_audio_config_update()
328 tmp = I915_READ(HSW_AUD_M_CTS_ENABLE(pipe)); in hsw_dp_audio_config_update()
[all …]
Di915_drv.c357 value = I915_READ(HUC_STATUS2) & HUC_FW_VERIFIED; in i915_getparam()
2141 s->wr_watermark = I915_READ(GEN7_WR_WATERMARK); in vlv_save_gunit_s0ix_state()
2142 s->gfx_prio_ctrl = I915_READ(GEN7_GFX_PRIO_CTRL); in vlv_save_gunit_s0ix_state()
2143 s->arb_mode = I915_READ(ARB_MODE); in vlv_save_gunit_s0ix_state()
2144 s->gfx_pend_tlb0 = I915_READ(GEN7_GFX_PEND_TLB0); in vlv_save_gunit_s0ix_state()
2145 s->gfx_pend_tlb1 = I915_READ(GEN7_GFX_PEND_TLB1); in vlv_save_gunit_s0ix_state()
2148 s->lra_limits[i] = I915_READ(GEN7_LRA_LIMITS(i)); in vlv_save_gunit_s0ix_state()
2150 s->media_max_req_count = I915_READ(GEN7_MEDIA_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
2151 s->gfx_max_req_count = I915_READ(GEN7_GFX_MAX_REQ_COUNT); in vlv_save_gunit_s0ix_state()
2153 s->render_hwsp = I915_READ(RENDER_HWS_PGA_GEN7); in vlv_save_gunit_s0ix_state()
[all …]
Di915_irq.c145 u32 val = I915_READ(reg); in gen5_assert_iir_is_zero()
186 val = I915_READ(PORT_HOTPLUG_EN); in i915_hotplug_interrupt_update_locked()
385 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events); in gen6_enable_rps_interrupts()
427 WARN_ON_ONCE(I915_READ(gen6_pm_iir(dev_priv)) & in gen9_enable_guc_interrupts()
468 old_val = I915_READ(GEN8_DE_PORT_IMR); in bdw_update_port_irq()
522 uint32_t sdeimr = I915_READ(SDEIMR); in ibx_display_interrupt_update()
542 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; in __i915_enable_pipestat()
569 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK; in __i915_disable_pipestat()
772 return I915_READ(PIPE_FRMCOUNT_G4X(pipe)); in g4x_get_vblank_counter()
966 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS)); in ironlake_rps_change_irq_handler()
[all …]
Dintel_device_info.c90 fuse = I915_READ(CHV_FUSE_GT); in cherryview_sseu_info_init()
134 fuse2 = I915_READ(GEN8_FUSE2); in gen9_sseu_info_init()
154 eu_disable = I915_READ(GEN9_EU_DISABLE(s)); in gen9_sseu_info_init()
235 fuse2 = I915_READ(GEN8_FUSE2); in broadwell_sseu_info_init()
245 eu_disable[0] = I915_READ(GEN8_EU_DISABLE0) & GEN8_EU_DIS0_S0_MASK; in broadwell_sseu_info_init()
246 eu_disable[1] = (I915_READ(GEN8_EU_DISABLE0) >> GEN8_EU_DIS0_S1_SHIFT) | in broadwell_sseu_info_init()
247 ((I915_READ(GEN8_EU_DISABLE1) & GEN8_EU_DIS1_S1_MASK) << in broadwell_sseu_info_init()
249 eu_disable[2] = (I915_READ(GEN8_EU_DISABLE1) >> GEN8_EU_DIS1_S2_SHIFT) | in broadwell_sseu_info_init()
250 ((I915_READ(GEN8_EU_DISABLE2) & GEN8_EU_DIS2_S2_MASK) << in broadwell_sseu_info_init()
352 u32 fuse_strap = I915_READ(FUSE_STRAP); in intel_device_info_runtime_init()
[all …]
Dintel_engine_cs.c163 cxt_size = I915_READ(GEN7_CXT_SIZE); in __intel_engine_context_size()
167 cxt_size = I915_READ(CXT_SIZE); in __intel_engine_context_size()
517 acthd = I915_READ(RING_ACTHD(engine->mmio_base)); in intel_engine_get_active_head()
519 acthd = I915_READ(ACTHD); in intel_engine_get_active_head()
533 bbaddr = I915_READ(RING_BBADDR(engine->mmio_base)); in intel_engine_get_last_batch_head()
600 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base)); in intel_engine_get_instdone()
605 instdone->slice_common = I915_READ(GEN7_SC_INSTDONE); in intel_engine_get_instdone()
616 instdone->instdone = I915_READ(RING_INSTDONE(mmio_base)); in intel_engine_get_instdone()
621 instdone->slice_common = I915_READ(GEN7_SC_INSTDONE); in intel_engine_get_instdone()
622 instdone->sampler[0][0] = I915_READ(GEN7_SAMPLER_INSTDONE); in intel_engine_get_instdone()
[all …]
Dintel_ddi.c782 if (I915_READ(reg) & DDI_BUF_IS_IDLE) in intel_wait_ddi_buf_idle()
893 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
901 temp = I915_READ(DP_TP_STATUS(PORT_E)); in hsw_fdi_link_train()
920 temp = I915_READ(DDI_BUF_CTL(PORT_E)); in hsw_fdi_link_train()
926 temp = I915_READ(DP_TP_CTL(PORT_E)); in hsw_fdi_link_train()
935 temp = I915_READ(FDI_RX_MISC(PIPE_A)); in hsw_fdi_link_train()
1019 wrpll = I915_READ(reg); in hsw_ddi_calc_wrpll_link()
1056 cfgcr1_val = I915_READ(cfgcr1_reg); in skl_calc_wrpll_link()
1057 cfgcr2_val = I915_READ(cfgcr2_reg); in skl_calc_wrpll_link()
1112 cfgcr0 = I915_READ(CNL_DPLL_CFGCR0(pll_id)); in cnl_calc_wrpll_link()
[all …]
Dintel_crt.c81 tmp = I915_READ(crt->adpa_reg); in intel_crt_get_hw_state()
104 tmp = I915_READ(crt->adpa_reg); in intel_crt_get_flags()
319 save_adpa = adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
341 adpa = I915_READ(crt->adpa_reg); in intel_ironlake_crt_detect_hotplug()
375 save_adpa = adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
391 adpa = I915_READ(crt->adpa_reg); in valleyview_crt_detect_hotplug()
449 stat = I915_READ(PORT_HOTPLUG_STAT); in intel_crt_detect_hotplug()
556 save_bclrpat = I915_READ(bclrpat_reg); in intel_crt_load_detect()
557 save_vtotal = I915_READ(vtotal_reg); in intel_crt_load_detect()
558 vblank = I915_READ(vblank_reg); in intel_crt_load_detect()
[all …]
Dintel_cdclk.c237 tmp = I915_READ(IS_MOBILE(dev_priv) ? HPLLVCO_MOBILE : HPLLVCO); in intel_hpll_vco()
405 uint32_t lcpll = I915_READ(LCPLL_CTL); in hsw_get_cdclk()
410 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) in hsw_get_cdclk()
485 WARN_ON(I915_READ(GCI_CONTROL) & PFI_CREDIT_RESEND); in vlv_program_pfi_credits()
630 uint32_t lcpll = I915_READ(LCPLL_CTL); in bdw_get_cdclk()
635 else if (I915_READ(FUSE_STRAP) & HSW_CDCLK_LIMIT) in bdw_get_cdclk()
654 if (WARN((I915_READ(LCPLL_CTL) & in bdw_set_cdclk()
671 val = I915_READ(LCPLL_CTL); in bdw_set_cdclk()
675 if (wait_for_us(I915_READ(LCPLL_CTL) & in bdw_set_cdclk()
679 val = I915_READ(LCPLL_CTL); in bdw_set_cdclk()
[all …]
Di915_gpu_error.c1043 error->fence[i] = I915_READ(FENCE_REG(i)); in i915_gem_record_fences()
1102 ee->semaphore_mboxes[0] = I915_READ(RING_SYNC_0(engine->mmio_base)); in gen6_record_semaphore_state()
1103 ee->semaphore_mboxes[1] = I915_READ(RING_SYNC_1(engine->mmio_base)); in gen6_record_semaphore_state()
1106 I915_READ(RING_SYNC_2(engine->mmio_base)); in gen6_record_semaphore_state()
1169 ee->rc_psmi = I915_READ(RING_PSMI_CTL(engine->mmio_base)); in error_record_engine_registers()
1170 ee->fault_reg = I915_READ(RING_FAULT_REG(engine)); in error_record_engine_registers()
1178 ee->faddr = I915_READ(RING_DMA_FADD(engine->mmio_base)); in error_record_engine_registers()
1179 ee->ipeir = I915_READ(RING_IPEIR(engine->mmio_base)); in error_record_engine_registers()
1180 ee->ipehr = I915_READ(RING_IPEHR(engine->mmio_base)); in error_record_engine_registers()
1181 ee->instps = I915_READ(RING_INSTPS(engine->mmio_base)); in error_record_engine_registers()
[all …]
Dintel_panel.c483 return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; in lpt_get_backlight()
490 return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in pch_get_backlight()
499 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; in i9xx_get_backlight()
518 return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; in _vlv_get_backlight()
534 return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller)); in bxt_get_backlight()
570 u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; in lpt_set_backlight()
580 tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; in pch_set_backlight()
608 tmp = I915_READ(BLC_PWM_CTL) & ~mask; in i9xx_set_backlight()
619 tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; in vlv_set_backlight()
732 tmp = I915_READ(BLC_PWM_CPU_CTL2); in lpt_disable_backlight()
[all …]
Dintel_runtime_pm.c322 ret = I915_READ(HSW_PWR_WELL_CTL_BIOS(id)) & req_mask ? 1 : 0; in hsw_power_well_requesters()
323 ret |= I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & req_mask ? 2 : 0; in hsw_power_well_requesters()
324 ret |= I915_READ(HSW_PWR_WELL_CTL_KVMR) & req_mask ? 4 : 0; in hsw_power_well_requesters()
325 ret |= I915_READ(HSW_PWR_WELL_CTL_DEBUG(id)) & req_mask ? 8 : 0; in hsw_power_well_requesters()
346 wait_for((disabled = !(I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & in hsw_wait_for_power_well_disable()
387 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); in hsw_power_well_enable()
406 val = I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)); in hsw_power_well_disable()
423 return (I915_READ(HSW_PWR_WELL_CTL_DRIVER(id)) & mask) == mask; in hsw_power_well_enabled()
430 WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9), in assert_can_enable_dc9()
432 WARN_ONCE(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5, in assert_can_enable_dc9()
[all …]
Dintel_pm.c63 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); in gen9_init_clock_gating()
77 I915_READ(CHICKEN_PAR1_1) & ~SKL_RC_HASH_OUTSIDE); in gen9_init_clock_gating()
80 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); in gen9_init_clock_gating()
84 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); in gen9_init_clock_gating()
88 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | in gen9_init_clock_gating()
93 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | in gen9_init_clock_gating()
98 I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) in gen9_init_clock_gating()
108 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
115 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | in bxt_init_clock_gating()
122 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | in bxt_init_clock_gating()
[all …]
Dintel_dpio_phy.c277 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
281 val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
286 val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
296 val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch)); in bxt_ddi_phy_set_signal_level()
301 val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch)); in bxt_ddi_phy_set_signal_level()
313 if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) in bxt_ddi_phy_is_enabled()
316 if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) & in bxt_ddi_phy_is_enabled()
324 if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { in bxt_ddi_phy_is_enabled()
336 u32 val = I915_READ(BXT_PORT_REF_DW6(phy)); in bxt_get_grc()
374 val = I915_READ(BXT_P_CR_GT_DISP_PWRON); in _bxt_ddi_phy_init()
[all …]
Dintel_display.c223 return ((I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2) * 10000; in intel_fdi_link_freq()
1015 line1 = I915_READ(reg) & line_mask; in pipe_scanline_is_moving()
1017 line2 = I915_READ(reg) & line_mask; in pipe_scanline_is_moving()
1084 val = I915_READ(DPLL(pipe)); in assert_pll()
1116 u32 val = I915_READ(TRANS_DDI_FUNC_CTL(cpu_transcoder)); in assert_fdi_tx()
1119 u32 val = I915_READ(FDI_TX_CTL(pipe)); in assert_fdi_tx()
1135 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx()
1157 val = I915_READ(FDI_TX_CTL(pipe)); in assert_fdi_tx_pll_enabled()
1167 val = I915_READ(FDI_RX_CTL(pipe)); in assert_fdi_rx_pll()
1188 port_sel = I915_READ(PP_ON_DELAYS(0)) & PANEL_PORT_SELECT_MASK; in assert_panel_unlocked()
[all …]
Dintel_psr.c69 val = I915_READ(VLV_PSRSTAT(pipe)) & in vlv_is_psr_active_on_pipe()
116 val = I915_READ(VLV_VSCSDP(pipe)); in vlv_psr_setup_vsc()
264 I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) | in vlv_psr_activate()
318 val |= I915_READ(EDP_PSR_CTL) & EDP_PSR_RESTORE_PSR_ACTIVE_CTX_MASK; in intel_enable_source_psr1()
412 I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) & in intel_psr_match_conditions()
466 WARN_ON(I915_READ(EDP_PSR2_CTL) & EDP_PSR2_ENABLE); in intel_psr_activate()
468 WARN_ON(I915_READ(EDP_PSR_CTL) & EDP_PSR_ENABLE); in intel_psr_activate()
606 val = I915_READ(VLV_PSRCTL(intel_crtc->pipe)); in vlv_psr_disable()
638 I915_READ(psr_ctl) & in hsw_psr_disable()
646 I915_READ(psr_ctl) & ~EDP_PSR_ENABLE); in hsw_psr_disable()
[all …]
Dintel_dvo.c129 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_connector_get_hw_state()
145 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_hw_state()
162 tmp = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_config()
184 u32 temp = I915_READ(dvo_reg); in intel_disable_dvo()
188 I915_READ(dvo_reg); in intel_disable_dvo()
198 u32 temp = I915_READ(dvo_reg); in intel_enable_dvo()
205 I915_READ(dvo_reg); in intel_enable_dvo()
274 dvo_val = I915_READ(dvo_reg) & in intel_dvo_pre_enable()
387 uint32_t dvo_val = I915_READ(intel_dvo->dev.dvo_reg); in intel_dvo_get_current_mode()
494 dpll[pipe] = I915_READ(DPLL(pipe)); in intel_dvo_init()
Dintel_lvds.c101 tmp = I915_READ(lvds_encoder->reg); in intel_lvds_get_hw_state()
126 tmp = I915_READ(lvds_encoder->reg); in intel_lvds_get_config()
144 tmp = I915_READ(PFIT_CONTROL); in intel_lvds_get_config()
157 pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; in intel_lvds_pps_get_hw_state()
159 val = I915_READ(PP_ON_DELAYS(0)); in intel_lvds_pps_get_hw_state()
167 val = I915_READ(PP_OFF_DELAYS(0)); in intel_lvds_pps_get_hw_state()
173 val = I915_READ(PP_DIVISOR(0)); in intel_lvds_pps_get_hw_state()
211 val = I915_READ(PP_CONTROL(0)); in intel_lvds_pps_init_hw()
314 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); in intel_enable_lvds()
316 I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); in intel_enable_lvds()
[all …]
Dintel_dsi_pll.c202 val = I915_READ(BXT_DSI_PLL_ENABLE); in bxt_dsi_pll_is_enabled()
216 val = I915_READ(BXT_DSI_PLL_CTL); in bxt_dsi_pll_is_enabled()
239 val = I915_READ(BXT_DSI_PLL_ENABLE); in bxt_disable_dsi_pll()
345 config->dsi_pll.ctrl = I915_READ(BXT_DSI_PLL_CTL); in bxt_dsi_get_pclk()
375 temp = I915_READ(MIPI_CTRL(port)); in vlv_dsi_reset_clocks()
444 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); in bxt_dsi_program_clocks()
554 val = I915_READ(BXT_DSI_PLL_ENABLE); in gen9lp_enable_dsi_pll()
624 tmp = I915_READ(BXT_MIPI_CLOCK_CTL); in gen9lp_dsi_reset_clocks()
631 tmp = I915_READ(MIPIO_TXESC_CLK_DIV1); in gen9lp_dsi_reset_clocks()
635 tmp = I915_READ(MIPIO_TXESC_CLK_DIV2); in gen9lp_dsi_reset_clocks()
Dintel_fifo_underrun.c91 u32 pipestat = I915_READ(reg) & 0xffff0000; in i9xx_check_fifo_underruns()
111 u32 pipestat = I915_READ(reg) & 0xffff0000; in i9xx_set_fifo_underrun_reporting()
141 uint32_t err_int = I915_READ(GEN7_ERR_INT); in ivybridge_check_fifo_underruns()
171 I915_READ(GEN7_ERR_INT) & ERR_INT_FIFO_UNDERRUN(pipe)) { in ivybridge_set_fifo_underrun_reporting()
207 uint32_t serr_int = I915_READ(SERR_INT); in cpt_check_pch_fifo_underruns()
239 if (old && I915_READ(SERR_INT) & in cpt_set_fifo_underrun_reporting()
Di915_vgpu.c212 mappable_base = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.base)); in intel_vgt_balloon()
213 mappable_size = I915_READ(vgtif_reg(avail_rs.mappable_gmadr.size)); in intel_vgt_balloon()
214 unmappable_base = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.base)); in intel_vgt_balloon()
215 unmappable_size = I915_READ(vgtif_reg(avail_rs.nonmappable_gmadr.size)); in intel_vgt_balloon()
Dintel_hdmi.c57 WARN(I915_READ(intel_hdmi->hdmi_reg) & enabled_bits, in assert_hdmi_port_disabled()
145 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_write_infoframe()
180 u32 val = I915_READ(VIDEO_DIP_CTL); in g4x_infoframe_enabled()
202 u32 val = I915_READ(reg); in ibx_write_infoframe()
239 u32 val = I915_READ(reg); in ibx_infoframe_enabled()
262 u32 val = I915_READ(reg); in cpt_write_infoframe()
300 u32 val = I915_READ(TVIDEO_DIP_CTL(pipe)); in cpt_infoframe_enabled()
320 u32 val = I915_READ(reg); in vlv_write_infoframe()
356 u32 val = I915_READ(VLV_TVIDEO_DIP_CTL(pipe)); in vlv_infoframe_enabled()
381 u32 val = I915_READ(ctl_reg); in hsw_write_infoframe()
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