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/arch/powerpc/platforms/512x/
Dclock-commonclk.c74 static struct clk *clks[MPC512x_CLK_LAST_PRIVATE]; variable
404 for (i = 0; i < ARRAY_SIZE(clks); i++) in mpc512x_clk_preset_data()
405 clks[i] = ERR_PTR(-ENODEV); in mpc512x_clk_preset_data()
447 clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1); in mpc512x_clk_setup_ref_clock()
448 calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]); in mpc512x_clk_setup_ref_clock()
462 clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq); in mpc512x_clk_setup_ref_clock()
651 div = clk_get_rate(clks[MPC512x_CLK_SYS]); in mpc512x_clk_setup_mclk()
652 div /= clk_get_rate(clks[MPC512x_CLK_IPS]); in mpc512x_clk_setup_mclk()
675 clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed( in mpc512x_clk_setup_mclk()
682 clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated( in mpc512x_clk_setup_mclk()
[all …]
/arch/arm/boot/dts/
Dimx27.dtsi73 clocks = <&clks IMX27_CLK_CPU_DIV>;
96 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
97 <&clks IMX27_CLK_DMA_AHB_GATE>;
107 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
114 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
115 <&clks IMX27_CLK_PER1_GATE>;
123 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
124 <&clks IMX27_CLK_PER1_GATE>;
132 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
133 <&clks IMX27_CLK_PER1_GATE>;
[all …]
Dimx25.dtsi86 clocks = <&clks 48>;
97 clocks = <&clks 48>;
107 clocks = <&clks 75>, <&clks 75>;
116 clocks = <&clks 76>, <&clks 76>;
125 clocks = <&clks 120>, <&clks 57>;
134 clocks = <&clks 121>, <&clks 57>;
144 clocks = <&clks 48>;
154 clocks = <&clks 51>;
165 clocks = <&clks 78>, <&clks 78>;
176 clocks = <&clks 102>;
[all …]
Dimx6sx.dtsi74 clocks = <&clks IMX6SX_CLK_ARM>,
75 <&clks IMX6SX_CLK_PLL2_PFD2>,
76 <&clks IMX6SX_CLK_STEP>,
77 <&clks IMX6SX_CLK_PLL1_SW>,
78 <&clks IMX6SX_CLK_PLL1_SYS>;
147 clocks = <&clks IMX6SX_CLK_OCRAM>;
170 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
181 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
182 <&clks IMX6SX_CLK_GPMI_APB>,
183 <&clks IMX6SX_CLK_GPMI_BCH>,
[all …]
Dimx6qdl.dtsi99 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
110 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
111 <&clks IMX6QDL_CLK_GPMI_APB>,
112 <&clks IMX6QDL_CLK_GPMI_BCH>,
113 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
114 <&clks IMX6QDL_CLK_PER1_BCH>;
128 clocks = <&clks IMX6QDL_CLK_HDMI_IAHB>,
129 <&clks IMX6QDL_CLK_HDMI_ISFR>;
155 clocks = <&clks IMX6QDL_CLK_TWD>;
188 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
[all …]
Dimx53.dtsi54 clocks = <&clks IMX5_CLK_ARM>;
120 clocks = <&clks IMX5_CLK_SATA_GATE>,
121 <&clks IMX5_CLK_SATA_REF>,
122 <&clks IMX5_CLK_AHB>;
133 clocks = <&clks IMX5_CLK_IPU_GATE>,
134 <&clks IMX5_CLK_IPU_DI0_GATE>,
135 <&clks IMX5_CLK_IPU_DI1_GATE>;
193 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
194 <&clks IMX5_CLK_DUMMY>,
195 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
[all …]
Dvfxxx.dtsi90 clocks = <&clks VF610_CLK_DMAMUX0>,
91 <&clks VF610_CLK_DMAMUX1>;
99 clocks = <&clks VF610_CLK_FLEXCAN0>,
100 <&clks VF610_CLK_FLEXCAN0>;
109 clocks = <&clks VF610_CLK_UART0>;
121 clocks = <&clks VF610_CLK_UART1>;
133 clocks = <&clks VF610_CLK_UART2>;
145 clocks = <&clks VF610_CLK_UART3>;
159 clocks = <&clks VF610_CLK_DSPI0>;
171 clocks = <&clks VF610_CLK_DSPI1>;
[all …]
Dimx51.dtsi85 clocks = <&clks IMX5_CLK_CPU_PODF>;
104 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
132 clocks = <&clks IMX5_CLK_IPU_GATE>,
133 <&clks IMX5_CLK_IPU_DI0_GATE>,
134 <&clks IMX5_CLK_IPU_DI1_GATE>;
171 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
172 <&clks IMX5_CLK_DUMMY>,
173 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
182 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
183 <&clks IMX5_CLK_DUMMY>,
[all …]
Dimx50.dtsi105 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
106 <&clks IMX5_CLK_DUMMY>,
107 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
117 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
118 <&clks IMX5_CLK_DUMMY>,
119 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
129 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
130 <&clks IMX5_CLK_UART3_PER_GATE>;
141 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
142 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
[all …]
Dimx35.dtsi70 clocks = <&clks 51>;
81 clocks = <&clks 53>;
90 clocks = <&clks 9>, <&clks 70>;
99 clocks = <&clks 9>, <&clks 71>;
110 clocks = <&clks 52>;
121 clocks = <&clks 68>;
134 clocks = <&clks 35 &clks 35>;
156 clocks = <&clks 9>, <&clks 72>;
168 clocks = <&clks 36 &clks 36>;
176 clocks = <&clks 46>, <&clks 8>;
[all …]
Dimx6ul.dtsi67 clocks = <&clks IMX6UL_CLK_ARM>,
68 <&clks IMX6UL_CLK_PLL2_BUS>,
69 <&clks IMX6UL_CLK_PLL2_PFD2>,
70 <&clks IMX6UL_CA7_SECONDARY_SEL>,
71 <&clks IMX6UL_CLK_STEP>,
72 <&clks IMX6UL_CLK_PLL1_SW>,
73 <&clks IMX6UL_CLK_PLL1_SYS>,
74 <&clks IMX6UL_PLL1_BYPASS>,
75 <&clks IMX6UL_CLK_PLL1>,
76 <&clks IMX6UL_PLL1_BYPASS_SRC>,
[all …]
Dimx6sl.dtsi58 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
59 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
60 <&clks IMX6SL_CLK_PLL1_SYS>;
105 clocks = <&clks IMX6SL_CLK_OCRAM>;
145 clocks = <&clks IMX6SL_CLK_SPDIF_GCLK>, <&clks IMX6SL_CLK_OSC>,
146 <&clks IMX6SL_CLK_SPDIF>, <&clks IMX6SL_CLK_DUMMY>,
147 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_DUMMY>,
148 <&clks IMX6SL_CLK_IPG>, <&clks IMX6SL_CLK_DUMMY>,
149 <&clks IMX6SL_CLK_DUMMY>, <&clks IMX6SL_CLK_SPBA>;
164 clocks = <&clks IMX6SL_CLK_ECSPI1>,
[all …]
Dimx1.dtsi49 clocks = <&clks IMX1_CLK_MCU>;
72 clocks = <&clks IMX1_CLK_HCLK>,
73 <&clks IMX1_CLK_PER1>;
81 clocks = <&clks IMX1_CLK_HCLK>,
82 <&clks IMX1_CLK_PER1>;
90 clocks = <&clks IMX1_CLK_DUMMY>,
91 <&clks IMX1_CLK_DUMMY>,
92 <&clks IMX1_CLK_PER2>;
101 clocks = <&clks IMX1_CLK_HCLK>,
102 <&clks IMX1_CLK_PER1>;
[all …]
Dimx6q.dtsi46 clocks = <&clks IMX6QDL_CLK_ARM>,
47 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
48 <&clks IMX6QDL_CLK_STEP>,
49 <&clks IMX6QDL_CLK_PLL1_SW>,
50 <&clks IMX6QDL_CLK_PLL1_SYS>;
84 clocks = <&clks IMX6QDL_CLK_OCRAM>;
95 clocks = <&clks IMX6Q_CLK_ECSPI5>,
96 <&clks IMX6Q_CLK_ECSPI5>;
149 clocks = <&clks IMX6QDL_CLK_SATA>,
150 <&clks IMX6QDL_CLK_SATA_REF_100M>,
[all …]
Dimx6dl.dtsi42 clocks = <&clks IMX6QDL_CLK_ARM>,
43 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
44 <&clks IMX6QDL_CLK_STEP>,
45 <&clks IMX6QDL_CLK_PLL1_SW>,
46 <&clks IMX6QDL_CLK_PLL1_SYS>;
66 clocks = <&clks IMX6QDL_CLK_OCRAM>;
97 clocks = <&clks IMX6DL_CLK_I2C4>;
118 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
119 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
120 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
Dimx7d.dtsi88 clocks = <&clks IMX7D_ARM_A7_ROOT_CLK>, <&clks IMX7D_ARM_A7_ROOT_SRC>,
89 <&clks IMX7D_PLL_ARM_MAIN_CLK>, <&clks IMX7D_PLL_SYS_MAIN_CLK>;
127 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
141 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
192 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
219 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
256 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
296 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
317 clocks = <&clks IMX7D_MAIN_AXI_ROOT_CLK>;
422 clocks = <&clks IMX7D_WDOG1_ROOT_CLK>;
[all …]
Dimx31.dtsi58 clocks = <&clks 10>, <&clks 30>;
67 clocks = <&clks 10>, <&clks 31>;
75 clocks = <&clks 10>, <&clks 49>;
85 clocks = <&clks 10>, <&clks 50>;
102 clocks = <&clks 10>, <&clks 48>;
111 clocks = <&clks 25>;
122 clks: ccm@53f80000{ label
133 clocks = <&clks 10>, <&clks 22>;
Dpxa27x.dtsi27 clocks = <&clks CLK_NONE>;
34 clocks = <&clks CLK_USBHOST>;
42 clocks = <&clks CLK_PWM0>;
49 clocks = <&clks CLK_PWM1>;
56 clocks = <&clks CLK_PWM0>;
63 clocks = <&clks CLK_PWM1>;
70 clocks = <&clks CLK_PWRI2C>;
80 clocks = <&clks CLK_USB>;
88 clocks = <&clks CLK_KEYPAD>;
101 clocks = <&clks CLK_CAMERA>;
[all …]
Datlas6.dtsi30 clocks = <&clks 12>;
66 clks: clock-controller@88000000 { label
87 clocks = <&clks 42>;
101 clocks = <&clks 5>;
108 clocks = <&clks 32>;
122 clocks = <&clks 34>;
133 clocks = <&clks 35>;
148 clocks = <&clks 32>;
162 clocks = <&clks 33>;
183 clocks = <&clks 9>;
[all …]
Dprima2.dtsi32 clocks = <&clks 12>;
77 clks: clock-controller@88000000 { label
98 clocks = <&clks 42>;
112 clocks = <&clks 5>;
119 clocks = <&clks 32>;
139 clocks = <&clks 35>;
154 clocks = <&clks 32>;
168 clocks = <&clks 33>;
189 clocks = <&clks 9>;
197 clocks = <&clks 8>;
[all …]
Dpxa3xx.dtsi23 clocks = <&clks CLK_PWRI2C>;
33 clocks = <&clks CLK_NAND>;
49 clocks = <&clks CLK_GPIO>;
62 clocks = <&clks CLK_MMC>;
73 clocks = <&clks CLK_MMC1>;
84 clocks = <&clks CLK_MMC2>;
95 clocks = <&clks CLK_USBHOST>;
109 clks: pxa3xx_clks@41300004 { label
120 clocks = <&clks CLK_OSTIMER>;
Daxm55xx.dtsi13 #include <dt-bindings/clock/lsi,axm5516-clks.h>
52 clks: clock-controller@2010020000 { label
53 compatible = "lsi,axm5516-clks";
119 clocks = <&clks AXXIA_CLK_PER>;
128 clocks = <&clks AXXIA_CLK_PER>;
137 clocks = <&clks AXXIA_CLK_PER>;
146 clocks = <&clks AXXIA_CLK_PER>;
163 clocks = <&clks AXXIA_CLK_PER>;
181 clocks = <&clks AXXIA_CLK_PER>;
192 clocks = <&clks AXXIA_CLK_PER>;
/arch/powerpc/boot/dts/
Dmpc5121.dtsi54 clocks = <&clks MPC512x_CLK_MBX_BUS>,
55 <&clks MPC512x_CLK_MBX_3D>,
56 <&clks MPC512x_CLK_MBX>;
71 clocks = <&clks MPC512x_CLK_NFC>;
138 clks: clock@f00 { label
163 clocks = <&clks MPC512x_CLK_BDLC>,
164 <&clks MPC512x_CLK_IPS>,
165 <&clks MPC512x_CLK_SYS>,
166 <&clks MPC512x_CLK_REF>,
167 <&clks MPC512x_CLK_MSCAN0_MCLK>;
[all …]
Dmpc5125twr.dts103 clks: clock@f00 { // Clock control label
133 clocks = <&clks MPC512x_CLK_BDLC>,
134 <&clks MPC512x_CLK_IPS>,
135 <&clks MPC512x_CLK_SYS>,
136 <&clks MPC512x_CLK_REF>,
137 <&clks MPC512x_CLK_MSCAN0_MCLK>;
145 clocks = <&clks MPC512x_CLK_BDLC>,
146 <&clks MPC512x_CLK_IPS>,
147 <&clks MPC512x_CLK_SYS>,
148 <&clks MPC512x_CLK_REF>,
[all …]
/arch/mips/ath79/
Dclock.c32 static struct clk *clks[3]; variable
34 .clks = clks,
35 .clk_num = ARRAY_SIZE(clks),
82 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate); in ar71xx_clocks_init()
83 clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate); in ar71xx_clocks_init()
84 clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate); in ar71xx_clocks_init()
118 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate); in ar724x_clocks_init()
119 clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate); in ar724x_clocks_init()
120 clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate); in ar724x_clocks_init()
151 clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate); in ar913x_clocks_init()
[all …]

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