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Searched refs:clks (Results 1 – 25 of 73) sorted by relevance

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/arch/arm/mach-imx/
Dclk-imx6sx.c93 static struct clk *clks[IMX6SX_CLK_CLK_END]; variable
145 clks[IMX6SX_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx6sx_clocks_init()
147 clks[IMX6SX_CLK_CKIL] = of_clk_get_by_name(ccm_node, "ckil"); in imx6sx_clocks_init()
148 clks[IMX6SX_CLK_OSC] = of_clk_get_by_name(ccm_node, "osc"); in imx6sx_clocks_init()
151 clks[IMX6SX_CLK_IPP_DI0] = of_clk_get_by_name(ccm_node, "ipp_di0"); in imx6sx_clocks_init()
152 clks[IMX6SX_CLK_IPP_DI1] = of_clk_get_by_name(ccm_node, "ipp_di1"); in imx6sx_clocks_init()
155 clks[IMX6SX_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); in imx6sx_clocks_init()
161 …clks[IMX6SX_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
162 …clks[IMX6SX_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
163 …clks[IMX6SX_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6sx_clocks_init()
[all …]
Dclk-imx6sl.c102 static struct clk *clks[IMX6SL_CLK_END]; variable
195 clks[IMX6SL_CLK_DUMMY] = imx_clk_fixed("dummy", 0); in imx6sl_clocks_init()
196 clks[IMX6SL_CLK_CKIL] = imx_obtain_fixed_clock("ckil", 0); in imx6sl_clocks_init()
197 clks[IMX6SL_CLK_OSC] = imx_obtain_fixed_clock("osc", 0); in imx6sl_clocks_init()
199 clks[IMX6SL_CLK_ANACLK1] = imx_obtain_fixed_clock("anaclk1", 0); in imx6sl_clocks_init()
206 …clks[IMX6SL_PLL1_BYPASS_SRC] = imx_clk_mux("pll1_bypass_src", base + 0x00, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
207 …clks[IMX6SL_PLL2_BYPASS_SRC] = imx_clk_mux("pll2_bypass_src", base + 0x30, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
208 …clks[IMX6SL_PLL3_BYPASS_SRC] = imx_clk_mux("pll3_bypass_src", base + 0x10, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
209 …clks[IMX6SL_PLL4_BYPASS_SRC] = imx_clk_mux("pll4_bypass_src", base + 0x70, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
210 …clks[IMX6SL_PLL5_BYPASS_SRC] = imx_clk_mux("pll5_bypass_src", base + 0xa0, 14, 1, pll_bypass_src_s… in imx6sl_clocks_init()
[all …]
Dclk.c10 void __init imx_check_clocks(struct clk *clks[], unsigned int count) in imx_check_clocks() argument
15 if (IS_ERR(clks[i])) in imx_check_clocks()
17 i, PTR_ERR(clks[i])); in imx_check_clocks()
/arch/powerpc/platforms/512x/
Dclock-commonclk.c73 static struct clk *clks[MPC512x_CLK_LAST_PRIVATE]; variable
403 for (i = 0; i < ARRAY_SIZE(clks); i++) in mpc512x_clk_preset_data()
404 clks[i] = ERR_PTR(-ENODEV); in mpc512x_clk_preset_data()
446 clks[MPC512x_CLK_REF] = mpc512x_clk_factor("ref", "osc", 1, 1); in mpc512x_clk_setup_ref_clock()
447 calc_freq = clk_get_rate(clks[MPC512x_CLK_REF]); in mpc512x_clk_setup_ref_clock()
461 clks[MPC512x_CLK_REF] = mpc512x_clk_fixed("ref", calc_freq); in mpc512x_clk_setup_ref_clock()
650 div = clk_get_rate(clks[MPC512x_CLK_SYS]); in mpc512x_clk_setup_mclk()
651 div /= clk_get_rate(clks[MPC512x_CLK_IPS]); in mpc512x_clk_setup_mclk()
674 clks[clks_idx_int + MCLK_IDX_MUX0] = mpc512x_clk_muxed( in mpc512x_clk_setup_mclk()
681 clks[clks_idx_int + MCLK_IDX_EN0] = mpc512x_clk_gated( in mpc512x_clk_setup_mclk()
[all …]
/arch/arm/boot/dts/
Dimx27.dtsi73 clocks = <&clks IMX27_CLK_CPU_DIV>;
96 clocks = <&clks IMX27_CLK_DMA_IPG_GATE>,
97 <&clks IMX27_CLK_DMA_AHB_GATE>;
107 clocks = <&clks IMX27_CLK_WDOG_IPG_GATE>;
114 clocks = <&clks IMX27_CLK_GPT1_IPG_GATE>,
115 <&clks IMX27_CLK_PER1_GATE>;
123 clocks = <&clks IMX27_CLK_GPT2_IPG_GATE>,
124 <&clks IMX27_CLK_PER1_GATE>;
132 clocks = <&clks IMX27_CLK_GPT3_IPG_GATE>,
133 <&clks IMX27_CLK_PER1_GATE>;
[all …]
Dimx6sx.dtsi73 clocks = <&clks IMX6SX_CLK_ARM>,
74 <&clks IMX6SX_CLK_PLL2_PFD2>,
75 <&clks IMX6SX_CLK_STEP>,
76 <&clks IMX6SX_CLK_PLL1_SW>,
77 <&clks IMX6SX_CLK_PLL1_SYS>;
145 clocks = <&clks IMX6SX_CLK_OCRAM>;
168 clocks = <&clks IMX6SX_CLK_APBH_DMA>;
179 clocks = <&clks IMX6SX_CLK_GPMI_IO>,
180 <&clks IMX6SX_CLK_GPMI_APB>,
181 <&clks IMX6SX_CLK_GPMI_BCH>,
[all …]
Dimx25.dtsi86 clocks = <&clks 48>;
97 clocks = <&clks 48>;
107 clocks = <&clks 75>, <&clks 75>;
116 clocks = <&clks 76>, <&clks 76>;
125 clocks = <&clks 120>, <&clks 57>;
134 clocks = <&clks 121>, <&clks 57>;
144 clocks = <&clks 48>;
154 clocks = <&clks 51>;
165 clocks = <&clks 78>, <&clks 78>;
176 clocks = <&clks 102>;
[all …]
Dimx53.dtsi108 clocks = <&clks IMX5_CLK_SATA_GATE>,
109 <&clks IMX5_CLK_SATA_REF>,
110 <&clks IMX5_CLK_AHB>;
121 clocks = <&clks IMX5_CLK_IPU_GATE>,
122 <&clks IMX5_CLK_IPU_DI0_GATE>,
123 <&clks IMX5_CLK_IPU_DI1_GATE>;
181 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
182 <&clks IMX5_CLK_DUMMY>,
183 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
193 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
[all …]
Dimx51.dtsi85 clocks = <&clks IMX5_CLK_CPU_PODF>;
104 clocks = <&clks IMX5_CLK_USB_PHY_GATE>;
132 clocks = <&clks IMX5_CLK_IPU_GATE>,
133 <&clks IMX5_CLK_IPU_DI0_GATE>,
134 <&clks IMX5_CLK_IPU_DI1_GATE>;
171 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
172 <&clks IMX5_CLK_DUMMY>,
173 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
182 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
183 <&clks IMX5_CLK_DUMMY>,
[all …]
Dimx50.dtsi105 clocks = <&clks IMX5_CLK_ESDHC1_IPG_GATE>,
106 <&clks IMX5_CLK_DUMMY>,
107 <&clks IMX5_CLK_ESDHC1_PER_GATE>;
117 clocks = <&clks IMX5_CLK_ESDHC2_IPG_GATE>,
118 <&clks IMX5_CLK_DUMMY>,
119 <&clks IMX5_CLK_ESDHC2_PER_GATE>;
129 clocks = <&clks IMX5_CLK_UART3_IPG_GATE>,
130 <&clks IMX5_CLK_UART3_PER_GATE>;
141 clocks = <&clks IMX5_CLK_ECSPI1_IPG_GATE>,
142 <&clks IMX5_CLK_ECSPI1_PER_GATE>;
[all …]
Dimx35.dtsi70 clocks = <&clks 51>;
81 clocks = <&clks 53>;
90 clocks = <&clks 9>, <&clks 70>;
99 clocks = <&clks 9>, <&clks 71>;
110 clocks = <&clks 52>;
121 clocks = <&clks 68>;
134 clocks = <&clks 35 &clks 35>;
156 clocks = <&clks 9>, <&clks 72>;
168 clocks = <&clks 36 &clks 36>;
176 clocks = <&clks 46>, <&clks 8>;
[all …]
Dvf610.dtsi106 clocks = <&clks VF610_CLK_DMAMUX0>,
107 <&clks VF610_CLK_DMAMUX1>;
114 clocks = <&clks VF610_CLK_FLEXCAN0>,
115 <&clks VF610_CLK_FLEXCAN0>;
124 clocks = <&clks VF610_CLK_UART0>;
136 clocks = <&clks VF610_CLK_UART1>;
148 clocks = <&clks VF610_CLK_UART2>;
160 clocks = <&clks VF610_CLK_UART3>;
174 clocks = <&clks VF610_CLK_DSPI0>;
184 clocks = <&clks VF610_CLK_SAI2>;
[all …]
Dimx6qdl.dtsi98 clocks = <&clks IMX6QDL_CLK_APBH_DMA>;
109 clocks = <&clks IMX6QDL_CLK_GPMI_IO>,
110 <&clks IMX6QDL_CLK_GPMI_APB>,
111 <&clks IMX6QDL_CLK_GPMI_BCH>,
112 <&clks IMX6QDL_CLK_GPMI_BCH_APB>,
113 <&clks IMX6QDL_CLK_PER1_BCH>;
125 clocks = <&clks IMX6QDL_CLK_TWD>;
158 clocks = <&clks IMX6QDL_CLK_PCIE_AXI>,
159 <&clks IMX6QDL_CLK_LVDS1_GATE>,
160 <&clks IMX6QDL_CLK_PCIE_REF_125M>;
[all …]
Dimx1.dtsi49 clocks = <&clks IMX1_CLK_MCU>;
72 clocks = <&clks IMX1_CLK_HCLK>,
73 <&clks IMX1_CLK_PER1>;
81 clocks = <&clks IMX1_CLK_HCLK>,
82 <&clks IMX1_CLK_PER1>;
90 clocks = <&clks IMX1_CLK_DUMMY>,
91 <&clks IMX1_CLK_DUMMY>,
92 <&clks IMX1_CLK_PER2>;
101 clocks = <&clks IMX1_CLK_HCLK>,
102 <&clks IMX1_CLK_PER1>;
[all …]
Dimx6dl.dtsi38 clocks = <&clks IMX6QDL_CLK_ARM>,
39 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
40 <&clks IMX6QDL_CLK_STEP>,
41 <&clks IMX6QDL_CLK_PLL1_SW>,
42 <&clks IMX6QDL_CLK_PLL1_SYS>;
62 clocks = <&clks IMX6QDL_CLK_OCRAM>;
93 clocks = <&clks IMX6DL_CLK_I2C4>;
110 clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>, <&clks IMX6QDL_CLK_LDB_DI1_SEL>,
111 <&clks IMX6QDL_CLK_IPU1_DI0_SEL>, <&clks IMX6QDL_CLK_IPU1_DI1_SEL>,
112 <&clks IMX6QDL_CLK_LDB_DI0>, <&clks IMX6QDL_CLK_LDB_DI1>;
Dimx6q.dtsi46 clocks = <&clks IMX6QDL_CLK_ARM>,
47 <&clks IMX6QDL_CLK_PLL2_PFD2_396M>,
48 <&clks IMX6QDL_CLK_STEP>,
49 <&clks IMX6QDL_CLK_PLL1_SW>,
50 <&clks IMX6QDL_CLK_PLL1_SYS>;
84 clocks = <&clks IMX6QDL_CLK_OCRAM>;
95 clocks = <&clks IMX6Q_CLK_ECSPI5>,
96 <&clks IMX6Q_CLK_ECSPI5>;
147 clocks = <&clks IMX6QDL_CLK_SATA>,
148 <&clks IMX6QDL_CLK_SATA_REF_100M>,
[all …]
Dimx6sl.dtsi58 clocks = <&clks IMX6SL_CLK_ARM>, <&clks IMX6SL_CLK_PLL2_PFD2>,
59 <&clks IMX6SL_CLK_STEP>, <&clks IMX6SL_CLK_PLL1_SW>,
60 <&clks IMX6SL_CLK_PLL1_SYS>;
104 clocks = <&clks IMX6SL_CLK_OCRAM>;
147 clocks = <&clks IMX6SL_CLK_ECSPI1>,
148 <&clks IMX6SL_CLK_ECSPI1>;
159 clocks = <&clks IMX6SL_CLK_ECSPI2>,
160 <&clks IMX6SL_CLK_ECSPI2>;
171 clocks = <&clks IMX6SL_CLK_ECSPI3>,
172 <&clks IMX6SL_CLK_ECSPI3>;
[all …]
Dimx31.dtsi58 clocks = <&clks 10>, <&clks 30>;
67 clocks = <&clks 10>, <&clks 31>;
75 clocks = <&clks 10>, <&clks 49>;
85 clocks = <&clks 10>, <&clks 50>;
102 clocks = <&clks 10>, <&clks 48>;
111 clocks = <&clks 25>;
114 clks: ccm@53f80000{ label
133 clocks = <&clks 10>, <&clks 22>;
Dprima2.dtsi32 clocks = <&clks 12>;
72 clks: clock-controller@88000000 { label
93 clocks = <&clks 42>;
107 clocks = <&clks 5>;
114 clocks = <&clks 32>;
134 clocks = <&clks 35>;
148 clocks = <&clks 32>;
162 clocks = <&clks 33>;
182 clocks = <&clks 9>;
189 clocks = <&clks 8>;
[all …]
Datlas6.dtsi30 clocks = <&clks 12>;
66 clks: clock-controller@88000000 { label
87 clocks = <&clks 42>;
101 clocks = <&clks 5>;
108 clocks = <&clks 32>;
122 clocks = <&clks 34>;
133 clocks = <&clks 35>;
147 clocks = <&clks 32>;
161 clocks = <&clks 33>;
182 clocks = <&clks 9>;
[all …]
Daxm55xx.dtsi13 #include <dt-bindings/clock/lsi,axm5516-clks.h>
52 clks: clock-controller@2010020000 { label
53 compatible = "lsi,axm5516-clks";
119 clocks = <&clks AXXIA_CLK_PER>;
128 clocks = <&clks AXXIA_CLK_PER>;
137 clocks = <&clks AXXIA_CLK_PER>;
146 clocks = <&clks AXXIA_CLK_PER>;
163 clocks = <&clks AXXIA_CLK_PER>;
181 clocks = <&clks AXXIA_CLK_PER>;
192 clocks = <&clks AXXIA_CLK_PER>;
Dimx28.dtsi92 clocks = <&clks 25>;
109 clocks = <&clks 50>;
121 clocks = <&clks 46>;
132 clocks = <&clks 47>;
143 clocks = <&clks 48>;
154 clocks = <&clks 49>;
909 clocks = <&clks 26>;
940 clocks = <&clks 55>;
950 clocks = <&clks 58>, <&clks 58>;
959 clocks = <&clks 59>, <&clks 59>;
[all …]
/arch/powerpc/boot/dts/
Dmpc5121.dtsi54 clocks = <&clks MPC512x_CLK_MBX_BUS>,
55 <&clks MPC512x_CLK_MBX_3D>,
56 <&clks MPC512x_CLK_MBX>;
71 clocks = <&clks MPC512x_CLK_NFC>;
139 clks: clock@f00 { label
164 clocks = <&clks MPC512x_CLK_BDLC>,
165 <&clks MPC512x_CLK_IPS>,
166 <&clks MPC512x_CLK_SYS>,
167 <&clks MPC512x_CLK_REF>,
168 <&clks MPC512x_CLK_MSCAN0_MCLK>;
[all …]
Dmpc5125twr.dts103 clks: clock@f00 { // Clock control label
133 clocks = <&clks MPC512x_CLK_BDLC>,
134 <&clks MPC512x_CLK_IPS>,
135 <&clks MPC512x_CLK_SYS>,
136 <&clks MPC512x_CLK_REF>,
137 <&clks MPC512x_CLK_MSCAN0_MCLK>;
145 clocks = <&clks MPC512x_CLK_BDLC>,
146 <&clks MPC512x_CLK_IPS>,
147 <&clks MPC512x_CLK_SYS>,
148 <&clks MPC512x_CLK_REF>,
[all …]
/arch/arm/mach-omap2/
Dclkt_clksel.c64 const struct clksel *clks; in _get_clksel_by_parent() local
69 for (clks = clk->clksel; clks->parent; clks++) in _get_clksel_by_parent()
70 if (clks->parent == src_clk) in _get_clksel_by_parent()
73 if (!clks->parent) { in _get_clksel_by_parent()
80 return clks; in _get_clksel_by_parent()
121 const struct clksel *clks; in _clksel_to_divisor() local
127 clks = _get_clksel_by_parent(clk, parent); in _clksel_to_divisor()
128 if (!clks) in _clksel_to_divisor()
131 for (clkr = clks->rates; clkr->div; clkr++) { in _clksel_to_divisor()
162 const struct clksel *clks; in _divisor_to_clksel() local
[all …]

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