| /drivers/net/wireless/bcmdhd/include/ |
| D | aidmp.h | 117 uint32 oobselina30; /* 0x000 */
118 uint32 oobselina74; /* 0x004 */
119 uint32 PAD[6];
120 uint32 oobselinb30; /* 0x020 */
121 uint32 oobselinb74; /* 0x024 */
122 uint32 PAD[6];
123 uint32 oobselinc30; /* 0x040 */
124 uint32 oobselinc74; /* 0x044 */
125 uint32 PAD[6];
126 uint32 oobselind30; /* 0x060 */
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| D | wlioctl.h | 68 uint32 num;
77 uint32 packetId;
90 uint32 channel;
101 uint32 flag;
120 uint32 version; /* version field */
121 uint32 length; /* byte length of data in this record,
138 uint32 ie_length; /* byte length of Information Elements */
153 uint32 version; /* version field */
154 uint32 length; /* byte length of data in this record,
173 uint32 nbss_cap; /* 802.11N BSS Capabilities (based on HT_CAP_*) */
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| D | sbchipc.h | 44 uint32 eci_output;
45 uint32 eci_control;
46 uint32 eci_inputlo;
47 uint32 eci_inputmi;
48 uint32 eci_inputhi;
49 uint32 eci_inputintpolaritylo;
50 uint32 eci_inputintpolaritymi;
51 uint32 eci_inputintpolarityhi;
52 uint32 eci_intmasklo;
53 uint32 eci_intmaskmi;
[all …]
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| D | siutils.h | 43 uint32 cccaps; /* chip common capabilities */
44 uint32 cccaps_ext; /* chip common capabilities extension */
46 uint32 pmucaps; /* pmu capabilities */
55 uint32 chipst; /* chip status */
127 typedef void (*gpio_handler_t)(uint32 stat, void *arg);
173 extern uint si_wrapperreg(si_t *sih, uint32 offset, uint32 mask, uint32 val);
174 extern uint si_core_wrapperreg(si_t *sih, uint32 coreidx, uint32 offset, uint32 mask, uint32 val);
176 extern uint32 si_core_cflags(si_t *sih, uint32 mask, uint32 val);
177 extern void si_core_cflags_wo(si_t *sih, uint32 mask, uint32 val);
178 extern uint32 si_core_sflags(si_t *sih, uint32 mask, uint32 val);
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| D | sbhnddma.h | 42 uint32 control; /* enable, et al */
43 uint32 addr; /* descriptor ring base address (4K aligned) */
44 uint32 ptr; /* last descriptor posted to chip */
45 uint32 status; /* current active descriptor, et al */
54 uint32 fifoaddr; /* diag address */
55 uint32 fifodatalow; /* low 32bits of data */
56 uint32 fifodatahigh; /* high 32bits of data */
57 uint32 pad; /* reserved */
65 uint32 ctrl; /* misc control bits & bufcount */
66 uint32 addr; /* data buffer address */
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| D | sbsdpcmdev.h | 41 uint32 PAD[2];
43 uint32 PAD[2];
50 uint32 PAD[92];
57 uint32 PAD[108];
64 uint32 PAD[116];
69 uint32 corecontrol; /* CoreControl, 0x000, rev8 */
70 uint32 corestatus; /* CoreStatus, 0x004, rev8 */
71 uint32 PAD[1];
72 uint32 biststatus; /* BistStatus, 0x00c, rev8 */
85 uint32 intstatus; /* IntStatus, 0x020, rev8 */
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| D | sbsocram.h | 41 uint32 coreinfo;
42 uint32 bwalloc;
43 uint32 extracoreinfo;
44 uint32 biststat;
45 uint32 bankidx;
46 uint32 standbyctrl;
48 uint32 errlogstatus; /* rev 6 */
49 uint32 errlogaddr; /* rev 6 */
51 uint32 cambankidx;
52 uint32 cambankstandbyctrl;
[all …]
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| D | sbconfig.h | 87 uint32 PAD[2];
88 uint32 sbipsflag; /* initiator port ocp slave flag */
89 uint32 PAD[3];
90 uint32 sbtpsflag; /* target port ocp slave flag */
91 uint32 PAD[11];
92 uint32 sbtmerrloga; /* (sonics >= 2.3) */
93 uint32 PAD;
94 uint32 sbtmerrlog; /* (sonics >= 2.3) */
95 uint32 PAD[3];
96 uint32 sbadmatch3; /* address match3 */
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| D | hndrte_armtrap.h | 64 uint32 type;
65 uint32 epc;
66 uint32 cpsr;
67 uint32 spsr;
68 uint32 r0; /* a1 */
69 uint32 r1; /* a2 */
70 uint32 r2; /* a3 */
71 uint32 r3; /* a4 */
72 uint32 r4; /* v1 */
73 uint32 r5; /* v2 */
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| D | bcmsdpcm.h | 175 uint32 cmd52rd; /* Cmd52RdCount, SDIO: cmd52 reads */
176 uint32 cmd52wr; /* Cmd52WrCount, SDIO: cmd52 writes */
177 uint32 cmd53rd; /* Cmd53RdCount, SDIO: cmd53 reads */
178 uint32 cmd53wr; /* Cmd53WrCount, SDIO: cmd53 writes */
179 uint32 abort; /* AbortCount, SDIO: aborts */
180 uint32 datacrcerror; /* DataCrcErrorCount, SDIO: frames w/CRC error */
181 uint32 rdoutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Rd Frm out of sync */
182 uint32 wroutofsync; /* RdOutOfSyncCount, SDIO/PCMCIA: Wr Frm out of sync */
183 uint32 writebusy; /* WriteBusyCount, SDIO: device asserted "busy" */
184 uint32 readwait; /* ReadWaitCount, SDIO: no data ready for a read cmd */
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| D | bcmendian.h | 42 ((uint32)((((uint32)(val) & (uint32)0x000000ffU) << 24) | \
43 (((uint32)(val) & (uint32)0x0000ff00U) << 8) | \
44 (((uint32)(val) & (uint32)0x00ff0000U) >> 8) | \
45 (((uint32)(val) & (uint32)0xff000000U) >> 24)))
49 ((uint32)((((uint32)(val) & (uint32)0x0000ffffU) << 16) | \
50 (((uint32)(val) & (uint32)0xffff0000U) >> 16)))
92 sizeof(*(ptr)) == sizeof(uint32) ? _LTOH32_UA((const uint8 *)(ptr)) : \
98 sizeof(*(ptr)) == sizeof(uint32) ? _NTOH32_UA((const uint8 *)(ptr)) : \
113 uint32 _val = (val); \
118 uint32 _val = (val); \
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| D | bcmsdh.h | 94 extern uint8 bcmsdh_cfg_read(void *sdh, uint func, uint32 addr, int *err);
95 extern void bcmsdh_cfg_write(void *sdh, uint func, uint32 addr, uint8 data, int *err);
98 extern uint32 bcmsdh_cfg_read_word(void *sdh, uint fnc_num, uint32 addr, int *err);
99 extern void bcmsdh_cfg_write_word(void *sdh, uint fnc_num, uint32 addr, uint32 data, int *err);
115 extern uint32 bcmsdh_reg_read(void *sdh, uint32 addr, uint size);
116 extern uint32 bcmsdh_reg_write(void *sdh, uint32 addr, uint size, uint32 data);
119 extern int bcmsdhsdio_set_sbaddr_window(void *sdh, uint32 address, bool force_set);
137 extern int bcmsdh_send_buf(void *sdh, uint32 addr, uint fn, uint flags,
140 extern int bcmsdh_recv_buf(void *sdh, uint32 addr, uint fn, uint flags,
164 extern int bcmsdh_rwdata(void *sdh, uint rw, uint32 addr, uint8 *buf, uint nbytes);
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| D | bcmsdspi.h | 61 uint32 caps; /* cached value of capabilities reg */
72 uint32 target_dev; /* Target device ID */
73 uint32 intmask; /* Current active interrupts */
76 uint32 controller_type; /* Host controller type */
79 uint32 intrcount; /* Client interrupts */
80 uint32 local_intrcount; /* Controller interrupts */
94 uint32 data_xfer_count; /* Current register transfer size */
95 uint32 cmd53_wr_data; /* Used to pass CMD53 write data */
96 uint32 card_response; /* Used to pass back response status byte */
97 uint32 card_rsp_data; /* Used to pass back response data word */
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| D | bcmutils.h | 117 uint32 requested; /* packets requested to be stored */
118 uint32 stored; /* packets stored */
119 uint32 saved; /* packets saved,
122 uint32 selfsaved; /* packets saved,
125 uint32 full_dropped; /* packets dropped,
128 uint32 dropped; /* packets dropped because pktq per that precedence is full */
129 uint32 sacrificed; /* packets dropped,
132 uint32 busy; /* packets droped because of hardware/transmission error */
133 uint32 retry; /* packets re-sent because they were not received */
134 uint32 ps_retry; /* packets retried again prior to moving power save mode */
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| D | trxhdr.h | 58 uint32 magic; /* "HDR0" */
59 uint32 len; /* Length of file including header */
60 uint32 crc32; /* 32-bit CRC from flag_version to end of file */
61 uint32 flag_version; /* 0:15 flags, 16:31 version */
63 uint32 offsets[TRX_MAX_OFFSET]; /* Offsets of partitions from start of header */
65 uint32 offsets[1]; /* Offsets of partitions from start of header */
78 #define SIZEOF_TRXHDR_V1 (sizeof(struct trx_header)+(TRX_V1_MAX_OFFSETS-1)*sizeof(uint32))
79 #define SIZEOF_TRXHDR_V2 (sizeof(struct trx_header)+(TRX_V2_MAX_OFFSETS-1)*sizeof(uint32))
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| /drivers/gpu/drm/vmwgfx/ |
| D | svga_reg.h | 278 #define SVGA_GMR_NULL ((uint32) -1)
279 #define SVGA_GMR_FRAMEBUFFER ((uint32) -2) /* Guest Framebuffer (GFB) */
283 uint32 ppn;
284 uint32 numPages;
289 uint32 gmrId;
290 uint32 offset;
318 uint32 bitsPerPixel : 8;
319 uint32 colorDepth : 8;
320 uint32 reserved : 16; /* Must be zero */
323 uint32 value;
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| D | svga3d_reg.h | 68 typedef uint32 SVGA3dBool; /* 32-bit Bool definition */
173 typedef uint32 SVGA3dColor; /* a, r, g, b */
290 uint32 value;
292 uint32 texture : 1;
293 uint32 volumeTexture : 1;
294 uint32 cubeTexture : 1;
295 uint32 offscreenRenderTarget : 1;
296 uint32 sameFormatRenderTarget : 1;
297 uint32 unknown1 : 1;
298 uint32 zStencil : 1;
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| D | svga_overlay.h | 67 uint32 cmdType;
68 uint32 streamId;
73 uint32 registerId;
74 uint32 value;
80 uint32 cmdType;
81 uint32 streamId;
91 uint32 command;
92 uint32 overlay;
104 uint32 regId;
105 uint32 value;
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| /drivers/video/ |
| D | au1200fb.h | 36 #define uint32 unsigned int macro
39 volatile uint32 reserved0;
40 volatile uint32 screen;
41 volatile uint32 backcolor;
42 volatile uint32 horztiming;
43 volatile uint32 verttiming;
44 volatile uint32 clkcontrol;
45 volatile uint32 pwmdiv;
46 volatile uint32 pwmhi;
47 volatile uint32 reserved1;
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| /drivers/net/wireless/bcmdhd/ |
| D | dhd_wlfc.h | 74 uint32 identifier;
77 uint32 push_time;
83 uint32 pushed;
84 uint32 popped;
85 uint32 failed_to_push;
86 uint32 failed_to_pop;
87 uint32 failed_slotfind;
88 uint32 slot_pos;
141 uint32 dstncredit_sent_packets;
142 uint32 dstncredit_acks;
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| D | siutils_priv.h | 42 typedef uint32 (*si_intrsoff_t)(void *intr_arg);
43 typedef void (*si_intrsrestore_t)(void *intr_arg, uint32 arg);
50 uint32 event;
82 uint32 coresba[SI_MAXCORES]; /* backplane address of each core */
84 uint32 coresba2[SI_MAXCORES]; /* address of each core second register set (usbh20) */
85 uint32 coresba_size[SI_MAXCORES]; /* backplane address space size */
86 uint32 coresba2_size[SI_MAXCORES]; /* second address space size */
90 uint32 wrapba[SI_MAXCORES]; /* address of controlling wrapper */
92 uint32 cia[SI_MAXCORES]; /* erom cia entry for each core */
93 uint32 cib[SI_MAXCORES]; /* erom cia entry for each core */
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| D | aiutils.c | 47 static uint32
48 get_erom_ent(si_t *sih, uint32 **eromptr, uint32 mask, uint32 match) in get_erom_ent()
50 uint32 ent; in get_erom_ent()
81 static uint32
82 get_asd(si_t *sih, uint32 **eromptr, uint sp, uint ad, uint st, uint32 *addrl, uint32 *addrh, in get_asd()
83 uint32 *sizel, uint32 *sizeh) in get_asd()
85 uint32 asd, sz, szd; in get_asd()
128 uint32 erombase, *eromptr, *eromlim; in ai_scan()
134 eromptr = (uint32 *)REG_MAP(erombase, SI_CORE_SIZE); in ai_scan()
148 eromptr = (uint32 *)(uintptr)erombase; in ai_scan()
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| D | sbutils.c | 44 static uint _sb_coreidx(si_info_t *sii, uint32 sba);
45 static uint _sb_scan(si_info_t *sii, uint32 sba, void *regs, uint bus, uint32 sbba,
47 static uint32 _sb_coresba(si_info_t *sii);
63 static uint32
64 sb_read_sbreg(si_info_t *sii, volatile uint32 *sbr) in sb_read_sbreg()
67 uint32 val, intr_val = 0; in sb_read_sbreg()
80 sbr = (volatile uint32 *)((uintptr)sbr & ~(1 << 11)); /* mask out bit 11 */ in sb_read_sbreg()
95 sb_write_sbreg(si_info_t *sii, volatile uint32 *sbr, uint32 v) in sb_write_sbreg()
98 volatile uint32 dummy; in sb_write_sbreg()
99 uint32 intr_val = 0; in sb_write_sbreg()
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| D | siutils.c | 55 static bool si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin,
61 static uint32 si_gpioreservation = 0;
101 static uint32 wd_msticks; /* watchdog timer ticks normalized to ms */
186 si_buscore_setup(si_info_t *sii, chipcregs_t *cc, uint bustype, uint32 savewin, in si_buscore_setup()
317 uint32 w, savewin; in si_doattach()
339 savewin = OSL_PCI_READ_CONFIG(sii->osh, PCI_BAR0_WIN, sizeof(uint32)); in si_doattach()
457 uint32 gpiopullup = 0, gpiopulldown = 0; in si_doattach()
569 return R_REG(sii->osh, ((uint32 *)(uintptr) in si_intflag()
852 uint32
867 uint32
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| /drivers/net/wireless/bcmdhd/common/include/proto/ |
| D | 802.11e.h | 62 uint32 min_srv_interval; /* Minimum Service Interval (us) */
63 uint32 max_srv_interval; /* Maximum Service Interval (us) */
64 uint32 inactivity_interval; /* Inactivity Interval (us) */
65 uint32 suspension_interval; /* Suspension Interval (us) */
66 uint32 srv_start_time; /* Service Start Time (us) */
67 uint32 min_data_rate; /* Minimum Data Rate (bps) */
68 uint32 mean_data_rate; /* Mean Data Rate (bps) */
69 uint32 peak_data_rate; /* Peak Data Rate (bps) */
70 uint32 max_burst_size; /* Maximum Burst Size (bytes) */
71 uint32 delay_bound; /* Delay Bound (us) */
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