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Searched refs:v16i1 (Results 1 – 25 of 161) sorted by relevance

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/external/llvm-project/llvm/lib/Target/X86/
DX86InstrVecCompiler.td171 def maskzeroupperv16i1 : maskzeroupper<v16i1, VK16>;
203 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
206 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
227 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
230 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
253 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
258 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
263 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
270 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
277 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86InstrVecCompiler.td171 def maskzeroupperv16i1 : maskzeroupper<v16i1, VK16>;
203 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
206 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
227 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
230 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
253 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
258 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
263 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
270 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
277 def : Pat<(v16i1 (insert_subvector (v16i1 immAllZerosV),
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb2/mve-intrinsics/
Dvclzcls-predicated.ll13 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
14 …%2 = tail call <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i1> %1, <16 …
55 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
56 …%2 = tail call <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i1> %1, <16 …
97 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
98 …%2 = tail call <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i1> %1, <16 …
130 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
133 declare <16 x i8> @llvm.arm.mve.cls.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>)
136 declare <16 x i8> @llvm.arm.mve.clz.predicated.v16i8.v16i1(<16 x i8>, <16 x i1>, <16 x i8>)
Dabsneg-predicated.ll14 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
15 …%2 = tail call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i1> %1, <16 …
56 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
57 …%2 = tail call <16 x i8> @llvm.arm.mve.mvn.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i1> %1, <16 …
126 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
127 …%2 = tail call <16 x i8> @llvm.arm.mve.neg.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i1> %1, <16 …
196 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
197 …%2 = tail call <16 x i8> @llvm.arm.mve.abs.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i1> %1, <16 …
238 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
239 …%2 = tail call <16 x i8> @llvm.arm.mve.qneg.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i1> %1, <16…
[all …]
Dvrev.ll13 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
14 …%2 = tail call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %a, i32 16, <16 x i1>…
27 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
28 …%2 = tail call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %a, i32 32, <16 x i1>…
69 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
70 …%2 = tail call <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8> %a, i32 64, <16 x i1>…
130 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
134 declare <16 x i8> @llvm.arm.mve.vrev.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>, <16 x i8>)
Dvminq.ll46 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
47 …%2 = tail call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 …
51 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
53 declare <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <1…
100 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
101 …%2 = tail call <16 x i8> @llvm.arm.mve.min.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 …
Dvmaxq.ll46 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
47 …%2 = tail call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 …
51 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
53 declare <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <1…
100 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
101 …%2 = tail call <16 x i8> @llvm.arm.mve.max.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32 …
Dvmulhq.ll49 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
50 …%2 = tail call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32…
54 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
56 declare <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <…
103 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
104 …%2 = tail call <16 x i8> @llvm.arm.mve.mulh.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32…
Dvrhaddq.ll49 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
50 …%2 = tail call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i3…
54 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
56 declare <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, …
103 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
104 …%2 = tail call <16 x i8> @llvm.arm.mve.rhadd.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i3…
Dvrmulhq.ll49 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
50 …%2 = tail call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i3…
54 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
56 declare <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, …
103 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
104 …%2 = tail call <16 x i8> @llvm.arm.mve.rmulh.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i3…
Dvector-shift-var.ll493 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
494 …%2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8>…
535 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
536 …%2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8>…
577 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
578 …%2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8>…
619 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
620 …%2 = call <16 x i8> @llvm.arm.mve.vshl.vector.predicated.v16i8.v16i8.v16i1(<16 x i8> %a, <16 x i8>…
661 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
662 …%2 = call <16 x i8> @llvm.arm.mve.vshl.scalar.predicated.v16i8.v16i1(<16 x i8> %a, i32 %b, i32 0, …
[all …]
Dvhaddq.ll49 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
50 …%2 = tail call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32…
54 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #1
56 declare <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>, <…
103 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
104 …%2 = tail call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, i32…
183 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
184 …%2 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %.splat, i32…
231 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
232 …%2 = call <16 x i8> @llvm.arm.mve.hadd.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %.splat, i32…
Dvabavq.ll4 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
12 declare i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x i1>)
85 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
86 …%2 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 0, i32 %a, <16 x i8> %b, <16 x i8> %c…
127 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
128 …%2 = call i32 @llvm.arm.mve.vabav.predicated.v16i8.v16i1(i32 1, i32 %a, <16 x i8> %b, <16 x i8> %c…
Dvmaxaq.ll55 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
56 …%2 = tail call <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <1…
60 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
62 declare <16 x i8> @llvm.arm.mve.vmaxa.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #2
Dvminaq.ll55 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
56 …%2 = tail call <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <1…
60 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
62 declare <16 x i8> @llvm.arm.mve.vmina.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>) #2
Dvmldav.ll4 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
12 declare i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32, i32, i32, i32, <16 x i8>, <16 x i8>, …
175 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
176 …%2 = call i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32 0, i32 0, i32 0, i32 %a, <16 x i8> …
217 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
218 …%2 = call i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32 1, i32 0, i32 0, i32 %a, <16 x i8> …
259 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
260 …%2 = call i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32 0, i32 0, i32 1, i32 %a, <16 x i8> …
301 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
302 …%2 = call i32 @llvm.arm.mve.vmldava.predicated.v16i8.v16i1(i32 0, i32 1, i32 0, i32 %a, <16 x i8> …
[all …]
Dvcaddq.ll4 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
14 declare <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32, i32, <16 x i8>, <16 x i8>, <16 x…
195 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
196 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> %inactive,…
237 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
238 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 0, <16 x i8> %inactive,…
307 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
308 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> %inactive,…
349 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
350 …%2 = call <16 x i8> @llvm.arm.mve.vcaddq.predicated.v16i8.v16i1(i32 1, i32 1, <16 x i8> %inactive,…
[all …]
Dvbrsrq.ll6 declare <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, i32, <16 x i1>)
11 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
44 %1 = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
45 …%2 = call <16 x i8> @llvm.arm.mve.vbrsr.predicated.v16i8.v16i1(<16 x i8> %inactive, <16 x i8> %a, …
Dveorq.ll56 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
57 …%2 = tail call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 …
61 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32) #2
63 declare <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8>, <16 x i8>, <16 x i1>, <16 x i…
128 %1 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %0)
129 …%2 = tail call <16 x i8> @llvm.arm.mve.eor.predicated.v16i8.v16i1(<16 x i8> %a, <16 x i8> %b, <16 …
/external/swiftshader/third_party/subzero/src/
DIceTypes.def49 X(v16i1, 4, 1, 16, i1, "<16 x i1>", "v16i1") \
77 X(v16i1, 1, 1, 0, 0, 1, 1, v16i1) \
78 X(v16i8, 1, 1, 0, 1, 0, 1, v16i1) \
/external/llvm-project/llvm/test/Transforms/InstCombine/ARM/
Dmve-v2i2v.ll8 declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>)
12 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
45 %int = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %vin)
46 %vout = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %int)
57 ; CHECK-NEXT: [[VOUT:%.*]] = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 [[INT]])
62 %vout = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %int)
82 ; CHECK-NEXT: [[INT:%.*]] = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> [[VIN:%.*]]), !range…
87 %int = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %vin)
123 %vec = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %iin)
124 %iout = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %vec)
[all …]
/external/llvm-project/llvm/test/CodeGen/Thumb2/
Dmve-pred-const.ll59 …%r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1 1, i1…
67 …%r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1 0, i1…
75 …%r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1…
170 %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 65535)
183 %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 0)
196 %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 43690)
225 %c = call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 43690)
226 %r = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> %c)
268 …%b = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1…
311 …%b = call i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1> <i1 0, i1 1, i1 0, i1 1, i1 0, i1 1, i1 0, i1…
[all …]
/external/llvm-project/llvm/test/Analysis/CostModel/ARM/
Dmve-active_lane_mask.ll28 …nstruction: %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i3…
31 %active.lane.mask = call <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32 %index, i32 %TC)
37 declare <16 x i1> @llvm.get.active.lane.mask.v16i1.i32(i32, i32)
/external/swiftshader/third_party/subzero/crosstest/
Dtest_select_main.cpp145 testSelect<v16si8, v16i1>(TotalTests, Passes, Failures); in main()
146 testSelect<v16ui8, v16i1>(TotalTests, Passes, Failures); in main()
149 testSelectI1<v16i1>(TotalTests, Passes, Failures); in main()
/external/llvm/include/llvm/CodeGen/
DMachineValueType.h62 v16i1 = 16, // 16 x i1 enumerator
229 SimpleTy == MVT::v16i1); in is16BitVector()
320 case v16i1: in getVectorElementType()
389 case v16i1: in getVectorNumElements()
456 case v16i1: in getSizeInBits()
596 if (NumElements == 16) return MVT::v16i1; in getVectorVT()

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