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Searched refs:ISD (Results 1 – 25 of 122) sorted by relevance

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/external/llvm/lib/CodeGen/SelectionDAG/
DSelectionDAGDumper.cpp36 if (getOpcode() < ISD::BUILTIN_OP_END) in getOperationName()
54 case ISD::DELETED_NODE: return "<<Deleted Node!>>"; in getOperationName()
56 case ISD::PREFETCH: return "Prefetch"; in getOperationName()
57 case ISD::MEMBARRIER: return "MemBarrier"; in getOperationName()
58 case ISD::ATOMIC_FENCE: return "AtomicFence"; in getOperationName()
59 case ISD::ATOMIC_CMP_SWAP: return "AtomicCmpSwap"; in getOperationName()
60 case ISD::ATOMIC_SWAP: return "AtomicSwap"; in getOperationName()
61 case ISD::ATOMIC_LOAD_ADD: return "AtomicLoadAdd"; in getOperationName()
62 case ISD::ATOMIC_LOAD_SUB: return "AtomicLoadSub"; in getOperationName()
63 case ISD::ATOMIC_LOAD_AND: return "AtomicLoadAnd"; in getOperationName()
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DLegalizeVectorOps.cpp154 if (Op.getOpcode() == ISD::LOAD) { in LegalizeOp()
156 ISD::LoadExtType ExtType = LD->getExtensionType(); in LegalizeOp()
157 if (LD->getMemoryVT().isVector() && ExtType != ISD::NON_EXTLOAD) { in LegalizeOp()
163 } else if (Op.getOpcode() == ISD::STORE) { in LegalizeOp()
193 case ISD::ADD: in LegalizeOp()
194 case ISD::SUB: in LegalizeOp()
195 case ISD::MUL: in LegalizeOp()
196 case ISD::SDIV: in LegalizeOp()
197 case ISD::UDIV: in LegalizeOp()
198 case ISD::SREM: in LegalizeOp()
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DLegalizeIntegerTypes.cpp50 case ISD::MERGE_VALUES:Res = PromoteIntRes_MERGE_VALUES(N, ResNo); break; in PromoteIntegerResult()
51 case ISD::AssertSext: Res = PromoteIntRes_AssertSext(N); break; in PromoteIntegerResult()
52 case ISD::AssertZext: Res = PromoteIntRes_AssertZext(N); break; in PromoteIntegerResult()
53 case ISD::BITCAST: Res = PromoteIntRes_BITCAST(N); break; in PromoteIntegerResult()
54 case ISD::BSWAP: Res = PromoteIntRes_BSWAP(N); break; in PromoteIntegerResult()
55 case ISD::BUILD_PAIR: Res = PromoteIntRes_BUILD_PAIR(N); break; in PromoteIntegerResult()
56 case ISD::Constant: Res = PromoteIntRes_Constant(N); break; in PromoteIntegerResult()
57 case ISD::CONVERT_RNDSAT: in PromoteIntegerResult()
59 case ISD::CTLZ_ZERO_UNDEF: in PromoteIntegerResult()
60 case ISD::CTLZ: Res = PromoteIntRes_CTLZ(N); break; in PromoteIntegerResult()
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DLegalizeDAG.cpp273 TLI.isLoadExtLegal(ISD::EXTLOAD, SVT) && in ExpandConstantFP()
286 DAG.getExtLoad(ISD::EXTLOAD, dl, OrigVT, in ExpandConstantFP()
303 assert(ST->getAddressingMode() == ISD::UNINDEXED && in ExpandUnalignedStore()
318 SDValue Result = DAG.getNode(ISD::BITCAST, dl, intVT, Val); in ExpandUnalignedStore()
359 StackPtr = DAG.getNode(ISD::ADD, dl, StackPtr.getValueType(), StackPtr, in ExpandUnalignedStore()
361 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, Increment); in ExpandUnalignedStore()
371 SDValue Load = DAG.getExtLoad(ISD::EXTLOAD, dl, RegVT, Store, StackPtr, in ExpandUnalignedStore()
383 DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &Stores[0], in ExpandUnalignedStore()
400 SDValue Hi = DAG.getNode(ISD::SRL, dl, VT, Val, ShiftAmount); in ExpandUnalignedStore()
407 Ptr = DAG.getNode(ISD::ADD, dl, Ptr.getValueType(), Ptr, in ExpandUnalignedStore()
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DTargetLowering.cpp104 ISD::CondCode &CCCode, in softenSetCCOperands()
112 case ISD::SETEQ: in softenSetCCOperands()
113 case ISD::SETOEQ: in softenSetCCOperands()
117 case ISD::SETNE: in softenSetCCOperands()
118 case ISD::SETUNE: in softenSetCCOperands()
122 case ISD::SETGE: in softenSetCCOperands()
123 case ISD::SETOGE: in softenSetCCOperands()
127 case ISD::SETLT: in softenSetCCOperands()
128 case ISD::SETOLT: in softenSetCCOperands()
132 case ISD::SETLE: in softenSetCCOperands()
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DDAGCombiner.cpp159 ISD::NodeType ExtType);
257 SDValue N3, ISD::CondCode CC,
259 SDValue SimplifySetCC(EVT VT, SDValue N0, SDValue N1, ISD::CondCode Cond,
402 if (Op.getOpcode() == ISD::FNEG) return 2; in isNegatibleForFree()
412 case ISD::ConstantFP: in isNegatibleForFree()
416 case ISD::FADD: in isNegatibleForFree()
422 !TLI.isOperationLegalOrCustom(ISD::FSUB, Op.getValueType())) in isNegatibleForFree()
432 case ISD::FSUB: in isNegatibleForFree()
439 case ISD::FMUL: in isNegatibleForFree()
440 case ISD::FDIV: in isNegatibleForFree()
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DLegalizeVectorTypes.cpp49 case ISD::MERGE_VALUES: R = ScalarizeVecRes_MERGE_VALUES(N, ResNo);break; in ScalarizeVectorResult()
50 case ISD::BITCAST: R = ScalarizeVecRes_BITCAST(N); break; in ScalarizeVectorResult()
51 case ISD::BUILD_VECTOR: R = ScalarizeVecRes_BUILD_VECTOR(N); break; in ScalarizeVectorResult()
52 case ISD::CONVERT_RNDSAT: R = ScalarizeVecRes_CONVERT_RNDSAT(N); break; in ScalarizeVectorResult()
53 case ISD::EXTRACT_SUBVECTOR: R = ScalarizeVecRes_EXTRACT_SUBVECTOR(N); break; in ScalarizeVectorResult()
54 case ISD::FP_ROUND: R = ScalarizeVecRes_FP_ROUND(N); break; in ScalarizeVectorResult()
55 case ISD::FP_ROUND_INREG: R = ScalarizeVecRes_InregOp(N); break; in ScalarizeVectorResult()
56 case ISD::FPOWI: R = ScalarizeVecRes_FPOWI(N); break; in ScalarizeVectorResult()
57 case ISD::INSERT_VECTOR_ELT: R = ScalarizeVecRes_INSERT_VECTOR_ELT(N); break; in ScalarizeVectorResult()
58 case ISD::LOAD: R = ScalarizeVecRes_LOAD(cast<LoadSDNode>(N));break; in ScalarizeVectorResult()
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DSelectionDAG.cpp98 bool ISD::isBuildVectorAllOnes(const SDNode *N) { in isBuildVectorAllOnes()
100 if (N->getOpcode() == ISD::BITCAST) in isBuildVectorAllOnes()
103 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isBuildVectorAllOnes()
108 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) in isBuildVectorAllOnes()
138 N->getOperand(i).getOpcode() != ISD::UNDEF) in isBuildVectorAllOnes()
146 bool ISD::isBuildVectorAllZeros(const SDNode *N) { in isBuildVectorAllZeros()
148 if (N->getOpcode() == ISD::BITCAST) in isBuildVectorAllZeros()
151 if (N->getOpcode() != ISD::BUILD_VECTOR) return false; in isBuildVectorAllZeros()
156 while (i != e && N->getOperand(i).getOpcode() == ISD::UNDEF) in isBuildVectorAllZeros()
178 N->getOperand(i).getOpcode() != ISD::UNDEF) in isBuildVectorAllZeros()
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DLegalizeFloatTypes.cpp60 case ISD::MERGE_VALUES:R = SoftenFloatRes_MERGE_VALUES(N, ResNo); break; in SoftenFloatResult()
61 case ISD::BITCAST: R = SoftenFloatRes_BITCAST(N); break; in SoftenFloatResult()
62 case ISD::BUILD_PAIR: R = SoftenFloatRes_BUILD_PAIR(N); break; in SoftenFloatResult()
63 case ISD::ConstantFP: in SoftenFloatResult()
66 case ISD::EXTRACT_VECTOR_ELT: in SoftenFloatResult()
68 case ISD::FABS: R = SoftenFloatRes_FABS(N); break; in SoftenFloatResult()
69 case ISD::FADD: R = SoftenFloatRes_FADD(N); break; in SoftenFloatResult()
70 case ISD::FCEIL: R = SoftenFloatRes_FCEIL(N); break; in SoftenFloatResult()
71 case ISD::FCOPYSIGN: R = SoftenFloatRes_FCOPYSIGN(N); break; in SoftenFloatResult()
72 case ISD::FCOS: R = SoftenFloatRes_FCOS(N); break; in SoftenFloatResult()
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/external/llvm/lib/Target/ARM/
DARMTargetTransformInfo.cpp177 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
178 assert(ISD && "Invalid opcode"); in getCastInstrCost()
183 { ISD::FP_ROUND, MVT::v2f64, 2 }, in getCastInstrCost()
184 { ISD::FP_EXTEND, MVT::v2f32, 2 }, in getCastInstrCost()
185 { ISD::FP_EXTEND, MVT::v4f32, 4 } in getCastInstrCost()
188 if (Src->isVectorTy() && ST->hasNEON() && (ISD == ISD::FP_ROUND || in getCastInstrCost()
189 ISD == ISD::FP_EXTEND)) { in getCastInstrCost()
192 ISD, LT.second); in getCastInstrCost()
207 { ISD::SIGN_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
208 { ISD::ZERO_EXTEND, MVT::v4i32, MVT::v4i16, 0 }, in getCastInstrCost()
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DARMISelLowering.cpp96 setOperationAction(ISD::LOAD, VT, Promote); in addTypeForNEON()
97 AddPromotedToType (ISD::LOAD, VT, PromotedLdStVT); in addTypeForNEON()
99 setOperationAction(ISD::STORE, VT, Promote); in addTypeForNEON()
100 AddPromotedToType (ISD::STORE, VT, PromotedLdStVT); in addTypeForNEON()
105 setOperationAction(ISD::SETCC, VT, Custom); in addTypeForNEON()
106 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
107 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Custom); in addTypeForNEON()
109 setOperationAction(ISD::SINT_TO_FP, VT, Custom); in addTypeForNEON()
110 setOperationAction(ISD::UINT_TO_FP, VT, Custom); in addTypeForNEON()
111 setOperationAction(ISD::FP_TO_SINT, VT, Custom); in addTypeForNEON()
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/external/llvm/lib/Target/R600/
DAMDGPUISelLowering.cpp37 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); in AMDGPUTargetLowering()
41 setOperationAction(ISD::FCEIL, MVT::f32, Legal); in AMDGPUTargetLowering()
42 setOperationAction(ISD::FEXP2, MVT::f32, Legal); in AMDGPUTargetLowering()
43 setOperationAction(ISD::FPOW, MVT::f32, Legal); in AMDGPUTargetLowering()
44 setOperationAction(ISD::FLOG2, MVT::f32, Legal); in AMDGPUTargetLowering()
45 setOperationAction(ISD::FABS, MVT::f32, Legal); in AMDGPUTargetLowering()
46 setOperationAction(ISD::FFLOOR, MVT::f32, Legal); in AMDGPUTargetLowering()
47 setOperationAction(ISD::FRINT, MVT::f32, Legal); in AMDGPUTargetLowering()
51 setOperationAction(ISD::STORE, MVT::f32, Promote); in AMDGPUTargetLowering()
52 AddPromotedToType(ISD::STORE, MVT::f32, MVT::i32); in AMDGPUTargetLowering()
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DAMDILISelLowering.cpp100 setOperationAction(ISD::SIGN_EXTEND_INREG, VT, Custom); in InitAMDILLowering()
101 setOperationAction(ISD::SUBE, VT, Expand); in InitAMDILLowering()
102 setOperationAction(ISD::SUBC, VT, Expand); in InitAMDILLowering()
103 setOperationAction(ISD::ADDE, VT, Expand); in InitAMDILLowering()
104 setOperationAction(ISD::ADDC, VT, Expand); in InitAMDILLowering()
105 setOperationAction(ISD::BRCOND, VT, Custom); in InitAMDILLowering()
106 setOperationAction(ISD::BR_JT, VT, Expand); in InitAMDILLowering()
107 setOperationAction(ISD::BRIND, VT, Expand); in InitAMDILLowering()
109 setOperationAction(ISD::SREM, VT, Expand); in InitAMDILLowering()
110 setOperationAction(ISD::SMUL_LOHI, VT, Expand); in InitAMDILLowering()
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DR600ISelLowering.cpp31 setOperationAction(ISD::MUL, MVT::i64, Expand); in R600TargetLowering()
38 setOperationAction(ISD::FADD, MVT::v4f32, Expand); in R600TargetLowering()
39 setOperationAction(ISD::FMUL, MVT::v4f32, Expand); in R600TargetLowering()
40 setOperationAction(ISD::FDIV, MVT::v4f32, Expand); in R600TargetLowering()
41 setOperationAction(ISD::FSUB, MVT::v4f32, Expand); in R600TargetLowering()
43 setOperationAction(ISD::ADD, MVT::v4i32, Expand); in R600TargetLowering()
44 setOperationAction(ISD::AND, MVT::v4i32, Expand); in R600TargetLowering()
45 setOperationAction(ISD::FP_TO_SINT, MVT::v4i32, Expand); in R600TargetLowering()
46 setOperationAction(ISD::FP_TO_UINT, MVT::v4i32, Expand); in R600TargetLowering()
47 setOperationAction(ISD::SINT_TO_FP, MVT::v4i32, Expand); in R600TargetLowering()
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/external/llvm/lib/Target/X86/
DX86TargetTransformInfo.cpp169 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getArithmeticInstrCost() local
170 assert(ISD && "Invalid opcode"); in getArithmeticInstrCost()
176 { ISD::MUL, MVT::v8i32, 4 }, in getArithmeticInstrCost()
177 { ISD::SUB, MVT::v8i32, 4 }, in getArithmeticInstrCost()
178 { ISD::ADD, MVT::v8i32, 4 }, in getArithmeticInstrCost()
179 { ISD::SUB, MVT::v4i64, 4 }, in getArithmeticInstrCost()
180 { ISD::ADD, MVT::v4i64, 4 }, in getArithmeticInstrCost()
186 { ISD::MUL, MVT::v4i64, 18 }, in getArithmeticInstrCost()
192 ISD, LT.second); in getArithmeticInstrCost()
201 { ISD::MUL, MVT::v2i64, 9 }, in getArithmeticInstrCost()
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DX86ISelLowering.cpp76 if (Vec.getOpcode() == ISD::UNDEF) in Extract128BitVector()
89 if (Vec.getOpcode() == ISD::BUILD_VECTOR) in Extract128BitVector()
90 return DAG.getNode(ISD::BUILD_VECTOR, dl, ResultVT, in Extract128BitVector()
94 SDValue Result = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, ResultVT, Vec, in Extract128BitVector()
109 if (Vec.getOpcode() == ISD::UNDEF) in Insert128BitVector()
127 return DAG.getNode(ISD::INSERT_SUBVECTOR, dl, ResultVT, Result, Vec, in Insert128BitVector()
237 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in X86TargetLowering()
248 setCondCodeAction(ISD::SETOEQ, MVT::f32, Expand); in X86TargetLowering()
249 setCondCodeAction(ISD::SETOEQ, MVT::f64, Expand); in X86TargetLowering()
250 setCondCodeAction(ISD::SETOEQ, MVT::f80, Expand); in X86TargetLowering()
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/external/llvm/lib/Target/Hexagon/
DHexagonISelLowering.cpp54 ISD::ArgFlagsTy ArgFlags, CCState &State);
59 ISD::ArgFlagsTy ArgFlags, CCState &State);
64 ISD::ArgFlagsTy ArgFlags, CCState &State);
69 ISD::ArgFlagsTy ArgFlags, CCState &State);
74 ISD::ArgFlagsTy ArgFlags, CCState &State);
79 ISD::ArgFlagsTy ArgFlags, CCState &State);
84 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon_VarArg()
133 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon()
171 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon32()
189 ISD::ArgFlagsTy ArgFlags, CCState &State) { in CC_Hexagon64()
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/external/llvm/lib/CodeGen/
DBasicTargetTransformInfo.cpp159 (TLI->isOperationLegalOrCustom(ISD::BR_JT, MVT::Other) || in shouldBuildLookupTables()
160 TLI->isOperationLegalOrCustom(ISD::BRIND, MVT::Other)); in shouldBuildLookupTables()
198 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getArithmeticInstrCost() local
199 assert(ISD && "Invalid opcode"); in getArithmeticInstrCost()
203 if (TLI->isOperationLegalOrPromote(ISD, LT.second)) { in getArithmeticInstrCost()
213 if (!TLI->isOperationExpand(ISD, LT.second)) { in getArithmeticInstrCost()
239 int ISD = TLI->InstructionOpcodeToISD(Opcode); in getCastInstrCost() local
240 assert(ISD && "Invalid opcode"); in getCastInstrCost()
263 if (TLI->isOperationLegalOrPromote(ISD, DstLT.second)) in getCastInstrCost()
274 if (!TLI->isOperationExpand(ISD, DstLT.second)) in getCastInstrCost()
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DAnalysis.cpp150 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { in getFCmpCondCode()
152 case FCmpInst::FCMP_FALSE: return ISD::SETFALSE; in getFCmpCondCode()
153 case FCmpInst::FCMP_OEQ: return ISD::SETOEQ; in getFCmpCondCode()
154 case FCmpInst::FCMP_OGT: return ISD::SETOGT; in getFCmpCondCode()
155 case FCmpInst::FCMP_OGE: return ISD::SETOGE; in getFCmpCondCode()
156 case FCmpInst::FCMP_OLT: return ISD::SETOLT; in getFCmpCondCode()
157 case FCmpInst::FCMP_OLE: return ISD::SETOLE; in getFCmpCondCode()
158 case FCmpInst::FCMP_ONE: return ISD::SETONE; in getFCmpCondCode()
159 case FCmpInst::FCMP_ORD: return ISD::SETO; in getFCmpCondCode()
160 case FCmpInst::FCMP_UNO: return ISD::SETUO; in getFCmpCondCode()
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DTargetLoweringBase.cpp591 static void InitCmpLibcallCCs(ISD::CondCode *CCs) { in InitCmpLibcallCCs()
592 memset(CCs, ISD::SETCC_INVALID, sizeof(ISD::CondCode)*RTLIB::UNKNOWN_LIBCALL); in InitCmpLibcallCCs()
593 CCs[RTLIB::OEQ_F32] = ISD::SETEQ; in InitCmpLibcallCCs()
594 CCs[RTLIB::OEQ_F64] = ISD::SETEQ; in InitCmpLibcallCCs()
595 CCs[RTLIB::OEQ_F128] = ISD::SETEQ; in InitCmpLibcallCCs()
596 CCs[RTLIB::UNE_F32] = ISD::SETNE; in InitCmpLibcallCCs()
597 CCs[RTLIB::UNE_F64] = ISD::SETNE; in InitCmpLibcallCCs()
598 CCs[RTLIB::UNE_F128] = ISD::SETNE; in InitCmpLibcallCCs()
599 CCs[RTLIB::OGE_F32] = ISD::SETGE; in InitCmpLibcallCCs()
600 CCs[RTLIB::OGE_F64] = ISD::SETGE; in InitCmpLibcallCCs()
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/external/llvm/lib/Target/Sparc/
DSparcISelLowering.cpp38 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_SRet()
51 ISD::ArgFlagsTy &ArgFlags, CCState &State) in CC_Sparc_Assign_f64()
82 const SmallVectorImpl<ISD::OutputArg> &Outs, in LowerReturn()
147 const SmallVectorImpl<ISD::InputArg> in LowerFormalArguments()
203 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments()
204 WholeValue = DAG.getNode(ISD::BITCAST, dl, MVT::f64, WholeValue); in LowerFormalArguments()
212 Arg = DAG.getNode(ISD::BITCAST, dl, MVT::f32, Arg); in LowerFormalArguments()
214 Arg = DAG.getNode(ISD::AssertSext, dl, MVT::i32, Arg, in LowerFormalArguments()
216 Arg = DAG.getNode(ISD::TRUNCATE, dl, VA.getLocVT(), Arg); in LowerFormalArguments()
258 DAG.getNode(ISD::BUILD_PAIR, dl, MVT::i64, LoVal, HiVal); in LowerFormalArguments()
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/external/llvm/lib/Target/MSP430/
DMSP430ISelLowering.cpp83 setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); in MSP430TargetLowering()
84 setIndexedLoadAction(ISD::POST_INC, MVT::i16, Legal); in MSP430TargetLowering()
86 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
87 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
88 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in MSP430TargetLowering()
89 setLoadExtAction(ISD::SEXTLOAD, MVT::i8, Expand); in MSP430TargetLowering()
90 setLoadExtAction(ISD::SEXTLOAD, MVT::i16, Expand); in MSP430TargetLowering()
95 setOperationAction(ISD::SRA, MVT::i8, Custom); in MSP430TargetLowering()
96 setOperationAction(ISD::SHL, MVT::i8, Custom); in MSP430TargetLowering()
97 setOperationAction(ISD::SRL, MVT::i8, Custom); in MSP430TargetLowering()
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/external/llvm/include/llvm/CodeGen/
DSelectionDAGNodes.h62 namespace ISD {
372 bool isTargetOpcode() const { return NodeType >= ISD::BUILTIN_OP_END; }
378 return NodeType >= ISD::FIRST_TARGET_MEMORY_OPCODE;
622 static const char* getIndexedModeName(ISD::MemIndexedMode AM);
892 : SDNode(ISD::HANDLENODE, DebugLoc(), getSDVTList(MVT::Other)) {
983 return getOperand(getOpcode() == ISD::STORE ? 2 : 1);
990 return N->getOpcode() == ISD::LOAD ||
991 N->getOpcode() == ISD::STORE ||
992 N->getOpcode() == ISD::PREFETCH ||
993 N->getOpcode() == ISD::ATOMIC_CMP_SWAP ||
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/external/llvm/lib/Target/AArch64/
DAArch64ISelLowering.cpp66 setTargetDAGCombine(ISD::ATOMIC_FENCE); in AArch64TargetLowering()
67 setTargetDAGCombine(ISD::ATOMIC_STORE); in AArch64TargetLowering()
70 setTargetDAGCombine(ISD::OR); in AArch64TargetLowering()
72 setTargetDAGCombine(ISD::AND); in AArch64TargetLowering()
73 setTargetDAGCombine(ISD::SRA); in AArch64TargetLowering()
76 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote); in AArch64TargetLowering()
77 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote); in AArch64TargetLowering()
78 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote); in AArch64TargetLowering()
81 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand); in AArch64TargetLowering()
82 setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand); in AArch64TargetLowering()
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/external/llvm/lib/Target/PowerPC/
DPPCISelDAGToDAG.cpp113 SDValue SelectCC(SDValue LHS, SDValue RHS, ISD::CondCode CC, DebugLoc dl);
127 N.getOpcode() == ISD::TargetGlobalAddress) { in SelectAddrImmOffs()
140 N.getOpcode() == ISD::TargetGlobalAddress) in SelectAddrIdxOffs()
288 if (N->getOpcode() != ISD::Constant) in isIntS16Immediate()
306 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i32) { in isInt32Immediate()
316 if (N->getOpcode() == ISD::Constant && N->getValueType(0) == MVT::i64) { in isInt64Immediate()
374 if (Opcode == ISD::SHL) { in isRotateAndMask()
379 } else if (Opcode == ISD::SRL) { in isRotateAndMask()
386 } else if (Opcode == ISD::ROTL) { in isRotateAndMask()
424 if (Op0Opc == ISD::AND && Op1Opc == ISD::AND) { in SelectBitfieldInsert()
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