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Searched refs:ResultReg (Results 1 – 25 of 43) sorted by relevance

12

/external/llvm-project/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp368 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca() local
370 ResultReg) in fastMaterializeAlloca()
374 return ResultReg; in fastMaterializeAlloca()
391 unsigned ResultReg = createResultReg(RC); in materializeInt() local
393 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
394 return ResultReg; in materializeInt()
427 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
429 TII.get(TargetOpcode::COPY), ResultReg) in materializeFP()
432 return ResultReg; in materializeFP()
445 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp368 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca() local
370 ResultReg) in fastMaterializeAlloca()
374 return ResultReg; in fastMaterializeAlloca()
391 unsigned ResultReg = createResultReg(RC); in materializeInt() local
393 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
394 return ResultReg; in materializeInt()
427 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
429 TII.get(TargetOpcode::COPY), ResultReg) in materializeFP()
432 return ResultReg; in materializeFP()
447 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
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/external/llvm/lib/Target/AArch64/
DAArch64FastISel.cpp323 unsigned ResultReg = createResultReg(&AArch64::GPR64spRegClass); in fastMaterializeAlloca() local
325 ResultReg) in fastMaterializeAlloca()
329 return ResultReg; in fastMaterializeAlloca()
346 unsigned ResultReg = createResultReg(RC); in materializeInt() local
348 ResultReg).addReg(ZeroReg, getKillRegState(true)); in materializeInt()
349 return ResultReg; in materializeInt()
383 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
385 TII.get(TargetOpcode::COPY), ResultReg) in materializeFP()
388 return ResultReg; in materializeFP()
403 unsigned ResultReg = createResultReg(TLI.getRegClassFor(VT)); in materializeFP() local
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/external/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp414 unsigned ResultReg = in selectBinaryOp() local
417 if (!ResultReg) in selectBinaryOp()
421 updateValueMap(I, ResultReg); in selectBinaryOp()
448 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, in selectBinaryOp() local
450 if (!ResultReg) in selectBinaryOp()
454 updateValueMap(I, ResultReg); in selectBinaryOp()
460 unsigned ResultReg = fastEmit_rf(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp() local
462 if (ResultReg) { in selectBinaryOp()
464 updateValueMap(I, ResultReg); in selectBinaryOp()
475 unsigned ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp() local
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/external/llvm-project/llvm/lib/Target/X86/
DX86FastISel.cpp88 unsigned &ResultReg, unsigned Alignment = 1);
97 unsigned &ResultReg);
318 MachineMemOperand *MMO, unsigned &ResultReg, in X86FastEmitLoad() argument
469 ResultReg = createResultReg(RC); in X86FastEmitLoad()
471 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); in X86FastEmitLoad()
706 unsigned &ResultReg) { in X86FastEmitExtend() argument
712 ResultReg = RR; in X86FastEmitExtend()
1346 unsigned ResultReg = 0; in X86SelectLoad() local
1347 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg, in X86SelectLoad()
1351 updateValueMap(I, ResultReg); in X86SelectLoad()
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/external/llvm/lib/Target/Mips/
DMipsFastISel.cpp133 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
279 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp() local
280 if (!ResultReg) in emitLogicalOp()
283 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
284 return ResultReg; in emitLogicalOp()
298 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca() local
300 ResultReg) in fastMaterializeAlloca()
303 return ResultReg; in fastMaterializeAlloca()
319 unsigned ResultReg = createResultReg(RC); in materialize32BitInt() local
323 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
DX86FastISel.cpp89 unsigned &ResultReg, unsigned Alignment = 1);
98 unsigned &ResultReg);
319 MachineMemOperand *MMO, unsigned &ResultReg, in X86FastEmitLoad() argument
470 ResultReg = createResultReg(RC); in X86FastEmitLoad()
472 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); in X86FastEmitLoad()
707 unsigned &ResultReg) { in X86FastEmitExtend() argument
713 ResultReg = RR; in X86FastEmitExtend()
1330 unsigned ResultReg = 0; in X86SelectLoad() local
1331 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg, in X86SelectLoad()
1335 updateValueMap(I, ResultReg); in X86SelectLoad()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/
DMipsFastISel.cpp181 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
329 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp() local
330 if (!ResultReg) in emitLogicalOp()
333 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
334 return ResultReg; in emitLogicalOp()
345 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca() local
347 ResultReg) in fastMaterializeAlloca()
350 return ResultReg; in fastMaterializeAlloca()
366 unsigned ResultReg = createResultReg(RC); in materialize32BitInt() local
370 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
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/external/llvm-project/llvm/lib/Target/Mips/
DMipsFastISel.cpp181 bool emitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
329 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in emitLogicalOp() local
330 if (!ResultReg) in emitLogicalOp()
333 emitInst(Opc, ResultReg).addReg(LHSReg).addReg(RHSReg); in emitLogicalOp()
334 return ResultReg; in emitLogicalOp()
345 unsigned ResultReg = createResultReg(&Mips::GPR32RegClass); in fastMaterializeAlloca() local
347 ResultReg) in fastMaterializeAlloca()
350 return ResultReg; in fastMaterializeAlloca()
366 unsigned ResultReg = createResultReg(RC); in materialize32BitInt() local
370 emitInst(Opc, ResultReg).addReg(Mips::ZERO).addImm(Imm); in materialize32BitInt()
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/external/llvm-project/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp627 Register ResultReg = in selectBinaryOp() local
630 if (!ResultReg) in selectBinaryOp()
634 updateValueMap(I, ResultReg); in selectBinaryOp()
661 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, in selectBinaryOp() local
663 if (!ResultReg) in selectBinaryOp()
667 updateValueMap(I, ResultReg); in selectBinaryOp()
677 Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp() local
679 if (!ResultReg) in selectBinaryOp()
685 updateValueMap(I, ResultReg); in selectBinaryOp()
961 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64)); in selectPatchpoint()
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/external/llvm/lib/Target/X86/
DX86FastISel.cpp89 unsigned &ResultReg, unsigned Alignment = 1);
98 unsigned &ResultReg);
349 MachineMemOperand *MMO, unsigned &ResultReg, in X86FastEmitLoad() argument
488 ResultReg = createResultReg(RC); in X86FastEmitLoad()
490 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg); in X86FastEmitLoad()
697 unsigned &ResultReg) { in X86FastEmitExtend() argument
703 ResultReg = RR; in X86FastEmitExtend()
1319 unsigned ResultReg = 0; in X86SelectLoad() local
1320 if (!X86FastEmitLoad(VT, AM, createMachineMemOperandFor(LI), ResultReg, in X86SelectLoad()
1324 updateValueMap(I, ResultReg); in X86SelectLoad()
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/SelectionDAG/
DFastISel.cpp613 unsigned ResultReg = in selectBinaryOp() local
616 if (!ResultReg) in selectBinaryOp()
620 updateValueMap(I, ResultReg); in selectBinaryOp()
647 unsigned ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, in selectBinaryOp() local
649 if (!ResultReg) in selectBinaryOp()
653 updateValueMap(I, ResultReg); in selectBinaryOp()
663 unsigned ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp() local
665 if (!ResultReg) in selectBinaryOp()
671 updateValueMap(I, ResultReg); in selectBinaryOp()
942 CLI.ResultReg = createResultReg(TLI.getRegClassFor(MVT::i64)); in selectPatchpoint()
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/external/llvm-project/llvm/lib/Target/WebAssembly/
DWebAssemblyFastISel.cpp591 unsigned ResultReg = createResultReg(MRI.getRegClass(Reg)); in copyValue() local
593 ResultReg) in copyValue()
595 return ResultReg; in copyValue()
603 unsigned ResultReg = in fastMaterializeAlloca() local
608 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeAlloca()
610 return ResultReg; in fastMaterializeAlloca()
622 unsigned ResultReg = in fastMaterializeConstant() local
627 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeConstant()
629 return ResultReg; in fastMaterializeConstant()
724 unsigned ResultReg = createResultReg(RC); in fastLowerArguments() local
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/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/
DWebAssemblyFastISel.cpp590 unsigned ResultReg = createResultReg(MRI.getRegClass(Reg)); in copyValue() local
592 ResultReg) in copyValue()
594 return ResultReg; in copyValue()
602 unsigned ResultReg = in fastMaterializeAlloca() local
607 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeAlloca()
609 return ResultReg; in fastMaterializeAlloca()
621 unsigned ResultReg = in fastMaterializeConstant() local
626 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeConstant()
628 return ResultReg; in fastMaterializeConstant()
712 unsigned ResultReg = createResultReg(RC); in fastLowerArguments() local
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/external/llvm/lib/Target/ARM/
DARMFastISel.cpp165 bool ARMEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
281 unsigned ResultReg = createResultReg(RC); in fastEmitInst_r() local
289 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
294 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_r()
297 return ResultReg; in fastEmitInst_r()
304 unsigned ResultReg = createResultReg(RC); in fastEmitInst_rr() local
314 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rr()
322 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_rr()
325 return ResultReg; in fastEmitInst_rr()
332 unsigned ResultReg = createResultReg(RC); in fastEmitInst_ri() local
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/external/llvm/lib/Target/WebAssembly/
DWebAssemblyFastISel.cpp516 unsigned ResultReg = createResultReg(MRI.getRegClass(Reg)); in copyValue() local
518 TII.get(WebAssembly::COPY), ResultReg) in copyValue()
520 return ResultReg; in copyValue()
528 unsigned ResultReg = createResultReg(Subtarget->hasAddr64() ? in fastMaterializeAlloca() local
534 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeAlloca()
536 return ResultReg; in fastMaterializeAlloca()
544 unsigned ResultReg = createResultReg(Subtarget->hasAddr64() ? in fastMaterializeConstant() local
550 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in fastMaterializeConstant()
552 return ResultReg; in fastMaterializeConstant()
606 unsigned ResultReg = createResultReg(RC); in fastLowerArguments() local
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/external/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp157 bool PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr,
443 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); in PPCSimplifyAddress() local
445 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0); in PPCSimplifyAddress()
446 Addr.Base.Reg = ResultReg; in PPCSimplifyAddress()
462 bool PPCFastISel::PPCEmitLoad(MVT VT, unsigned &ResultReg, Address &Addr, in PPCEmitLoad() argument
476 (ResultReg ? MRI.getRegClass(ResultReg) : in PPCEmitLoad()
524 bool IsVSSRC = (ResultReg != 0) && isVSSRCRegister(ResultReg); in PPCEmitLoad()
525 bool IsVSFRC = (ResultReg != 0) && isVSFRCRegister(ResultReg); in PPCEmitLoad()
534 if (ResultReg == 0) in PPCEmitLoad()
535 ResultReg = createResultReg(UseRC); in PPCEmitLoad()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/
DARMFastISel.cpp195 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
304 Register ResultReg = createResultReg(RC); in fastEmitInst_r() local
312 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
317 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_r()
320 return ResultReg; in fastEmitInst_r()
327 unsigned ResultReg = createResultReg(RC); in fastEmitInst_rr() local
337 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rr()
345 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_rr()
348 return ResultReg; in fastEmitInst_rr()
355 unsigned ResultReg = createResultReg(RC); in fastEmitInst_ri() local
[all …]
/external/llvm-project/llvm/lib/Target/ARM/
DARMFastISel.cpp194 bool ARMEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
303 Register ResultReg = createResultReg(RC); in fastEmitInst_r() local
311 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill)); in fastEmitInst_r()
316 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_r()
319 return ResultReg; in fastEmitInst_r()
326 unsigned ResultReg = createResultReg(RC); in fastEmitInst_rr() local
336 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II, ResultReg) in fastEmitInst_rr()
344 TII.get(TargetOpcode::COPY), ResultReg) in fastEmitInst_rr()
347 return ResultReg; in fastEmitInst_rr()
354 unsigned ResultReg = createResultReg(RC); in fastEmitInst_ri() local
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/external/llvm-project/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp166 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
436 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); in PPCSimplifyAddress() local
438 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0); in PPCSimplifyAddress()
439 Addr.Base.Reg = ResultReg; in PPCSimplifyAddress()
455 bool PPCFastISel::PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr, in PPCEmitLoad() argument
470 (ResultReg ? MRI.getRegClass(ResultReg) : in PPCEmitLoad()
526 if (ResultReg == 0) in PPCEmitLoad()
527 ResultReg = createResultReg(UseRC); in PPCEmitLoad()
542 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in PPCEmitLoad()
550 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in PPCEmitLoad()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
DPPCFastISel.cpp165 bool PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr,
435 unsigned ResultReg = createResultReg(&PPC::G8RC_and_G8RC_NOX0RegClass); in PPCSimplifyAddress() local
437 ResultReg).addFrameIndex(Addr.Base.FI).addImm(0); in PPCSimplifyAddress()
438 Addr.Base.Reg = ResultReg; in PPCSimplifyAddress()
454 bool PPCFastISel::PPCEmitLoad(MVT VT, Register &ResultReg, Address &Addr, in PPCEmitLoad() argument
469 (ResultReg ? MRI.getRegClass(ResultReg) : in PPCEmitLoad()
525 if (ResultReg == 0) in PPCEmitLoad()
526 ResultReg = createResultReg(UseRC); in PPCEmitLoad()
541 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in PPCEmitLoad()
549 BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(Opc), ResultReg) in PPCEmitLoad()
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/external/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp2682 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in lowerScalarAbs() local
2688 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg) in lowerScalarAbs()
2692 MRI.replaceRegWith(Dest.getReg(), ResultReg); in lowerScalarAbs()
2693 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in lowerScalarAbs()
2833 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBCNT() local
2846 BuildMI(MBB, MII, DL, InstDesc, ResultReg) in splitScalar64BitBCNT()
2850 MRI.replaceRegWith(Dest.getReg(), ResultReg); in splitScalar64BitBCNT()
2854 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in splitScalar64BitBCNT()
2878 unsigned ResultReg = MRI.createVirtualRegister(&AMDGPU::VReg_64RegClass); in splitScalar64BitBFE() local
2889 BuildMI(MBB, MII, DL, get(TargetOpcode::REG_SEQUENCE), ResultReg) in splitScalar64BitBFE()
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/external/llvm/include/llvm/CodeGen/
DFastISel.h80 unsigned ResultReg; member
96 ResultReg(0), NumResultRegs(0), IsPatchPoint(false) {} in CallLoweringInfo()
/external/llvm-project/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp5781 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in moveScalarAddSub() local
5795 MRI.replaceRegWith(OldDstReg, ResultReg); in moveScalarAddSub()
5798 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in moveScalarAddSub()
5862 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in lowerSelect() local
5865 BuildMI(MBB, MII, DL, get(AMDGPU::V_CNDMASK_B32_e64), ResultReg) in lowerSelect()
5872 MRI.replaceRegWith(Dest.getReg(), ResultReg); in lowerSelect()
5874 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in lowerSelect()
5887 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in lowerScalarAbs() local
5896 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg) in lowerScalarAbs()
5900 MRI.replaceRegWith(Dest.getReg(), ResultReg); in lowerScalarAbs()
[all …]
/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/
DSIInstrInfo.cpp5121 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in moveScalarAddSub() local
5135 MRI.replaceRegWith(OldDstReg, ResultReg); in moveScalarAddSub()
5138 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in moveScalarAddSub()
5155 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in lowerScalarAbs() local
5164 BuildMI(MBB, MII, DL, get(AMDGPU::V_MAX_I32_e64), ResultReg) in lowerScalarAbs()
5168 MRI.replaceRegWith(Dest.getReg(), ResultReg); in lowerScalarAbs()
5169 addUsersToMoveToVALUWorklist(ResultReg, MRI, Worklist); in lowerScalarAbs()
5544 Register ResultReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass); in splitScalar64BitBCNT() local
5555 BuildMI(MBB, MII, DL, InstDesc, ResultReg).add(SrcRegSub1).addReg(MidReg); in splitScalar64BitBCNT()
5557 MRI.replaceRegWith(Dest.getReg(), ResultReg); in splitScalar64BitBCNT()
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