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/external/u-boot/board/Marvell/guruplug/
Dkwbimage.cfg22 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
25 # bit24: 1= enable exit self refresh mode on DDR access
30 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
41 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
52 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
59 DATA 0xFFD01410 0x000000cc # DDR Address Control
74 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000C52 # DDR Mode
[all …]
/external/u-boot/board/Seagate/goflexhome/
Dkwbimage.cfg28 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
31 # bit24: 1= enable exit self refresh mode on DDR access
36 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
47 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
58 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
65 DATA 0xFFD01410 0x0000000d # DDR Address Control
80 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
84 DATA 0xFFD01418 0x00000000 # DDR Operation
85 # bit3-0: 0x0, DDR cmd
88 DATA 0xFFD0141C 0x00000C52 # DDR Mode
[all …]
/external/u-boot/board/Marvell/sheevaplug/
Dkwbimage.cfg22 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
25 # bit24: 1= enable exit self refresh mode on DDR access
30 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
41 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
52 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
59 DATA 0xFFD01410 0x000000cc # DDR Address Control
74 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000C52 # DDR Mode
[all …]
/external/u-boot/board/Synology/ds109/
Dkwbimage.cfg26 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
29 # bit24: 1= enable exit self refresh mode on DDR access
34 DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
45 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
56 DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
63 DATA 0xFFD01410 0x0000000d # DDR Address Control
78 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
82 DATA 0xFFD01418 0x00000000 # DDR Operation
83 # bit3-0: 0x0, DDR cmd
86 DATA 0xFFD0141C 0x00000C52 # DDR Mode
[all …]
/external/u-boot/board/Seagate/dockstar/
Dkwbimage.cfg25 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
28 # bit24: 1= enable exit self refresh mode on DDR access
33 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
44 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
55 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
62 DATA 0xFFD01410 0x0000000d # DDR Address Control
77 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
81 DATA 0xFFD01418 0x00000000 # DDR Operation
82 # bit3-0: 0x0, DDR cmd
85 DATA 0xFFD0141C 0x00000C52 # DDR Mode
[all …]
/external/u-boot/board/Marvell/dreamplug/
Dkwbimage.cfg23 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
26 # bit24: 1= enable exit self refresh mode on DDR access
31 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
42 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
53 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
60 DATA 0xFFD01410 0x000000cc # DDR Address Control
75 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
79 DATA 0xFFD01418 0x00000000 # DDR Operation
80 # bit3-0: 0x0, DDR cmd
83 DATA 0xFFD0141C 0x00000C52 # DDR Mode
[all …]
/external/u-boot/board/Seagate/nas220/
Dkwbimage.cfg27 DATA 0xFFD01400 0x43000618 # DDR Configuration register
30 # bit24: 1= enable exit self refresh mode on DDR access
35 DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
46 DATA 0xFFD01408 0x11012227 # DDR Timing (Low) (active cycles value +1)
56 DATA 0xFFD0140C 0x00000819 # DDR Timing (High)
64 DATA 0xFFD01410 0x0000000d # DDR Address Control
79 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
83 DATA 0xFFD01418 0x00000000 # DDR Operation
84 # bit3-0: 0x0, DDR cmd
87 DATA 0xFFD0141C 0x00000632 # DDR Mode
[all …]
/external/u-boot/board/Marvell/openrd/
Dkwbimage.cfg22 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
25 # bit24: 1= enable exit self refresh mode on DDR access
30 DATA 0xFFD01404 0x37543000 # DDR Controller Control Low
41 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
52 DATA 0xFFD0140C 0x00000a33 # DDR Timing (High)
59 DATA 0xFFD01410 0x000000cc # DDR Address Control
74 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000C52 # DDR Mode
[all …]
/external/u-boot/board/LaCie/netspace_v2/
Dkwbimage-is2.cfg23 DATA 0xFFD01400 0x43000618 # DDR Configuration register
26 # bit24: 1= enable exit self refresh mode on DDR access
31 DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
42 DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
52 DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
59 DATA 0xFFD01410 0x00000008 # DDR Address Control
74 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000632 # DDR Mode
[all …]
Dkwbimage.cfg23 DATA 0xFFD01400 0x43000618 # DDR Configuration register
26 # bit24: 1= enable exit self refresh mode on DDR access
31 DATA 0xFFD01404 0x35143000 # DDR Controller Control Low
42 DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
52 DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
59 DATA 0xFFD01410 0x0000000C # DDR Address Control
74 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000632 # DDR Mode
[all …]
Dkwbimage-ns2l.cfg23 DATA 0xFFD01400 0x43000618 # DDR Configuration register
26 # bit24: 1= enable exit self refresh mode on DDR access
31 DATA 0xFFD01404 0x34143000 # DDR Controller Control Low
42 DATA 0xFFD01408 0x11012228 # DDR Timing (Low) (active cycles value +1)
52 DATA 0xFFD0140C 0x00000A19 # DDR Timing (High)
59 DATA 0xFFD01410 0x0000DDDD # DDR Address Control
74 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000632 # DDR Mode
[all …]
/external/u-boot/board/iomega/iconnect/
Dkwbimage.cfg22 DATA 0xffd01400 0x43000c30 # DDR Configuration register
25 # bit24: 0x1, enable exit self refresh mode on DDR access
30 DATA 0xffd01404 0x37543000 # DDR Controller Control Low
41 DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
52 DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
59 DATA 0xffd01410 0x000000cc # DDR Address Control
74 DATA 0xffd01414 0x00000000 # DDR Open Pages Control
78 DATA 0xffd01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xffd0141c 0x00000c52 # DDR Mode
[all …]
/external/u-boot/board/LaCie/net2big_v2/
Dkwbimage.cfg23 DATA 0xFFD01400 0x43000C30 # DDR Configuration register
26 # bit24: 1= enable exit self refresh mode on DDR access
31 DATA 0xFFD01404 0x38743000 # DDR Controller Control Low
42 DATA 0xFFD01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
52 DATA 0xFFD0140C 0x00000A32 # DDR Timing (High)
59 DATA 0xFFD01410 0x0000CCCC # DDR Address Control
74 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
78 DATA 0xFFD01418 0x00000000 # DDR Operation
79 # bit3-0: 0x0, DDR cmd
82 DATA 0xFFD0141C 0x00000662 # DDR Mode
[all …]
/external/u-boot/board/cloudengines/pogo_e02/
Dkwbimage.cfg26 DATA 0xffd01400 0x43000c30 # DDR Configuration register
29 # bit24: 1= enable exit self refresh mode on DDR access
34 DATA 0xffd01404 0x37543000 # DDR Controller Control Low
45 DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
56 DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
63 DATA 0xffd01410 0x000000cc # DDR Address Control
78 DATA 0xffd01414 0x00000000 # DDR Open Pages Control
82 DATA 0xffd01418 0x00000000 # DDR Operation
83 # bit3-0: 0x0, DDR cmd
86 DATA 0xffd0141c 0x00000c52 # DDR Mode
[all …]
/external/u-boot/board/raidsonic/ib62x0/
Dkwbimage.cfg23 DATA 0xffd01400 0x43000c30 # DDR Configuration register
26 # bit24: 0x1, enable exit self refresh mode on DDR access
31 DATA 0xffd01404 0x37543000 # DDR Controller Control Low
42 DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
53 DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
60 DATA 0xffd01410 0x0000000c # DDR Address Control
75 DATA 0xffd01414 0x00000000 # DDR Open Pages Control
79 DATA 0xffd01418 0x00000000 # DDR Operation
80 # bit3-0: 0x0, DDR cmd
83 DATA 0xffd0141c 0x00000c52 # DDR Mode
[all …]
/external/u-boot/board/keymile/km_arm/
Dkwbimage.cfg45 # bit24: 1= enable exit self refresh mode on DDR access
50 DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
62 DATA 0xFFD01408 0x34136552 # DDR Timing (Low) (active cycles value +1)
73 DATA 0xFFD0140C 0x00000033 # DDR Timing (High)
80 DATA 0xFFD01410 0x0000000D # DDR Address Control
95 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
99 DATA 0xFFD01418 0x00000000 # DDR Operation
100 # bit3-0: 0x0, DDR cmd
103 DATA 0xFFD0141C 0x00000652 # DDR Mode
104 DATA 0xFFD01420 0x00000044 # DDR Extended Mode
[all …]
Dkwbimage-memphis.cfg48 # bit24: 1= enable exit self refresh mode on DDR access
53 DATA 0xFFD01404 0x38543000 # DDR Controller Control Low
65 DATA 0xFFD01408 0x2302433E # DDR Timing (Low) (active cycles value +1)
76 DATA 0xFFD0140C 0x00000A3E # DDR Timing (High)
83 DATA 0xFFD01410 0x00000001 # DDR Address Control
98 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
102 DATA 0xFFD01418 0x00000000 # DDR Operation
103 # bit3-0: 0x0, DDR cmd
106 DATA 0xFFD0141C 0x00000652 # DDR Mode
107 DATA 0xFFD01420 0x00000006 # DDR Extended Mode
[all …]
Dkwbimage_128M16_1.cfg97 # bit 24: 1, enable exit self refresh mode on DDR access
102 DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
118 DATA 0xFFD01408 0x2302444e # DDR Timing (Low) (active cycles value +1)
129 DATA 0xFFD0140C 0x0000003e # DDR Timing (High)
136 DATA 0xFFD01410 0x00000001 # DDR Address Control
151 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
155 DATA 0xFFD01418 0x00000000 # DDR Operation
156 # bit 3-0: 0, DDR cmd
159 DATA 0xFFD0141C 0x00000652 # DDR Mode
170 DATA 0xFFD01420 0x00000006 # DDR Extended Mode
[all …]
Dkwbimage_256M8_1.cfg97 # bit 24: 1, enable exit self refresh mode on DDR access
102 DATA 0xFFD01404 0x36543000 # DDR Controller Control Low
118 DATA 0xFFD01408 0x2202444E # DDR Timing (Low) (active cycles value +1)
129 DATA 0xFFD0140C 0x0000003E # DDR Timing (High)
136 DATA 0xFFD01410 0x00000000 # DDR Address Control
151 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
155 DATA 0xFFD01418 0x00000000 # DDR Operation
156 # bit 3-0: 0, DDR cmd
159 DATA 0xFFD0141C 0x00000652 # DDR Mode
170 DATA 0xFFD01420 0x00000006 # DDR Extended Mode
[all …]
/external/u-boot/doc/
DREADME.ramboot-ppc85xx4 RAMBOOT literally means boot from DDR. But since DDR is volatile memory some
5 pre-mechanism is required to load the DDR with the bootloader binary.
9 which can initialize the DDR and get the complete bootloader copied to DDR.
11 In addition to the above there could be some more methods to initialize the DDR
15 1. Load the RAM based bootloader onto DDR via JTAG/BDI interface. And then
16 execute the bootloader from DDR.
22 2. Load the RAM based bootloader onto DDR using already existing bootloader on
23 the board.And then execute the bootloader from DDR.
29 In this case you can get your test bootloader binary into DDR via tftp
51 Preconfigure DDR/L2SRAM through JTAG interface.
[all …]
/external/u-boot/board/freescale/ls1012ardb/
DKconfig37 hex "PFE DDR physical base address"
41 hex "PFE DDR base address"
45 hex "PFE DDR base address"
49 hex "PFE DDR base address"
89 hex "PFE DDR physical base address"
93 hex "PFE DDR base address"
97 hex "PFE DDR base address"
101 hex "PFE DDR base address"
/external/u-boot/board/renesas/sh7785lcr/
DREADME.sh7785lcr28 0x08000000 - 0x0bffffff(CS2) | USB | DDR SDRAM
29 0x0c000000 - 0x0fffffff(CS3) | SD | DDR SDRAM
33 0x40000000 - 0x5fffffff | DDR SDRAM | (cannot use)
45 address mode. This mode can use 128MB DDR-SDRAM.
48 extended address mode. This mode can use 384MB DDR-SDRAM. And if you run
49 "pmb" command, this mode can use 512MB DDR-SDRAM.
55 0x88000000 | 0x48000000 | 384MB | DDR-SDRAM (Cacheable)
59 0xa8000000 | 0x48000000 | 384MB | DDR-SDRAM (Non-cacheable)
64 0x80000000 | 0x40000000 | 512MB | DDR-SDRAM (Cacheable)
65 0xa0000000 | 0x40000000 | 512MB | DDR-SDRAM (Non-cacheable)
[all …]
/external/u-boot/board/buffalo/lsxl/
Dkwbimage-lsxhl.cfg26 # DDR Configuration register
30 # bit24: 1, enable exit self refresh mode on DDR access
35 # DDR Controller Control Low
53 # DDR Timing (Low)
65 # DDR Timing (High)
73 # DDR Address Control
89 # DDR Open Pages Control
94 # DDR Operation
99 # DDR Mode
110 # DDR Extended Mode
[all …]
Dkwbimage-lschl.cfg26 # DDR Configuration register
30 # bit24: 1, enable exit self refresh mode on DDR access
35 # DDR Controller Control Low
53 # DDR Timing (Low)
65 # DDR Timing (High)
73 # DDR Address Control
89 # DDR Open Pages Control
94 # DDR Operation
99 # DDR Mode
110 # DDR Extended Mode
[all …]
/external/u-boot/board/d-link/dns325/
Dkwbimage.cfg26 DATA 0xFFD01400 0x43000c30 # DDR Configuration register
29 # bit24: 1, enable exit self refresh mode on DDR access
34 DATA 0xFFD01404 0x39543000 # DDR Controller Control Low
51 DATA 0xFFD01408 0x22125451 # DDR Timing (Low)
62 DATA 0xFFD0140C 0x00000833 # DDR Timing (High)
69 DATA 0xFFD01410 0x0000000c # DDR Address Control
84 DATA 0xFFD01414 0x00000000 # DDR Open Pages Control
88 DATA 0xFFD01418 0x00000000 # DDR Operation
92 DATA 0xFFD0141C 0x00000C52 # DDR Mode
102 DATA 0xFFD01420 0x00000040 # DDR Extended Mode
[all …]

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